Patents Examined by David Lam
  • Semiconductor memory device and memory system configured to perform tracking read on first memory cells followed by shift read on second memory cells using read voltage correction value determined during the tracking read
    Patent number: 10643715
    Abstract: A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 5, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Konno, Yoshikazu Harada, Kosuke Yanagidaira, Jun Nakai, Hiroe Kami, Yuko Utsunomiya
  • Adapting flash memory programming parameters for high endurance and steady performance
    Patent number: 10643730
    Abstract: The present embodiments relate to methods for maintaining steady and high performance programming of non-volatile memory devices such as NAND-type flash devices. According to certain aspects, embodiments provide adaptive control of programming parameters over the lifespan of a NAND flash device so as to maintain write performance and obtain high endurance.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Avi Steiner, Hanan Weingarten, Yasuhiko Kurosawa
  • Negative kick on bit line control transistors for faster bit line settling during sensing
    Patent number: 10643677
    Abstract: A memory device and associated techniques improve a settling time of bit lines in a memory device during a read or verify operation. Bit line control (BLC) transistors in the sense circuits are briefly turned off during a sensing process. After the read voltage on a selected word line is changed to a second word line level or higher, a control gate voltage of the BLC transistor is lowered. This helps to inhibit a current flow from a sense circuit through a bit line when a voltage of the bit line is settling. The voltage of the bit line may be settling in response to a memory cell coupled to the selected word line undergoing a transition from off to on. A settling time of the bit line is shortened by stopping the current flow from the sense circuit. The transition of the memory cell from off to on is also improved.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 5, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Hiroki Yabe
  • Smart home scene switching method and system
    Patent number: 10637679
    Abstract: A smart home scene switching method and system are disclosed. In the method and system, a priority order of several scenes is calculated dynamically according to status parameters of a current scene and/or historical record of past scenes, and scenes are sequentially switched according to the priority order, based on an event causing scene change and a switching rule between the event and the scene. The smart home scene switching method and system expand switching and selecting of smart home scenes. The scenes are switched according to the priority order, thus simplifying user's switching and selecting operation on scenes and further improving the efficiency of switching scenes, which improves the reliability and stability of smart home scene switching.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 28, 2020
    Assignee: ZHUHAI UNILINK TECHNOLOGY CO., LTD.
    Inventors: Shuqiang Jin, Yongqiang Zhang, Jiamin Wang
  • Semiconductor memory device that includes a block decoder having plural transistors and a latch circuit
    Patent number: 10629268
    Abstract: A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.
    Type: Grant
    Filed: September 2, 2018
    Date of Patent: April 21, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koji Kato, Hitoshi Shiga
  • Three-dimensional semiconductor device with top dummy cells and bottom dummy cells and operating method thereof
    Patent number: 10622040
    Abstract: Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing a soft program operation on a top dummy cell and a bottom dummy cell, among dummy cells stacked in a vertical direction, by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cell and a second soft program voltage greater than the first soft program voltage to a top dummy word line coupled to the top dummy cell formed above the bottom dummy cell.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Phase change memory device with reduced read disturb and method of making the same
    Patent number: 10622063
    Abstract: A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 14, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Michael Grobis, Zhaoqiang Bai, Ward Parkinson
  • Sensing charge recycling circuitry
    Patent number: 10614876
    Abstract: A memory device include one or more sections of memory banks. Each of the one or more sections may include multiple sensing amplifiers and a digit line to supply voltages to the sensing amplifiers during a refresh of the respective section. The memory device may also include transmission circuitry configured to transmit excess charge remaining on a first digit line of a first section to a second digit line of a second section after a refresh of the first section and before a refresh of the second section.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Smith
  • Stochastic switching device with adjustable randomness
    Patent number: 10607674
    Abstract: A two-terminal stochastic switch is disclosed. The switch includes a magnetic tunnel junction (MTJ) stack, an access switch controlled by a first terminal and coupled to the MTJ stack, such that when the access switch is on, electrical current flows from a first source coupled to the MTJ stack, through the MTJ stack, and through the access switch to a second source, and a digital buffer coupled to the MTJ stack and the access switch which is configured to transform an analog signal associated with a voltage division across the MTJ stack and the access switch to a digital signal, output of the digital buffer forming a second terminal.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 31, 2020
    Assignees: Purdue Research Foundation, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kerem Yunus Camsari, Supriyo Datta, Sayeef Salahuddin
  • Programming of memory devices responsive to a stored representation of a programming voltage indicative of a programming efficiency
    Patent number: 10586597
    Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Silvia Beltrami, Angelo Visconti
  • Partial program operation of memory wordline
    Patent number: 10580495
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a memory module comprising non-volatile memory. Here, the memory module is configured to program a page of non-volatile memory with a first number of program cycles and indicate (e.g., to a host) that the page is partially programmed. The memory module is also configured to program the page with a second number of program cycles after a predetermined time, wherein the memory module performs one or more other storage operations during the predetermined time, and indicate (e.g., to the host) that the page is fully programmed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 3, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Refael Ben-Rubi, Mark Shlick
  • Sensing operations in memory by comparing inputs in a sense amplifier
    Patent number: 10573372
    Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can include an array of memory cells; and a controller coupled to the array configured to sense a first memory cell based upon a first input associated with the memory cell and a second input and a third input associated with a second memory cell.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Takamasa Suzuki
  • Memory device including heterogeneous volatile memory chips and electronic device including the same
    Patent number: 10559550
    Abstract: A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jungbae Lee, Kwanghyun Kim, Sang-Kyu Kang, Do Kyun Kim, DongMin Kim, Ji Hyun Ahn
  • Memory device having selectable memory block pairs
    Patent number: 10559330
    Abstract: A memory device may include a first half memory block, a second half memory block, a row decoder group, and a read/write circuit which may be disposed between the first half memory block and the second half memory block. The read/write circuit may be coupled to the first half memory block and the second half memory block through a first bit line and a second bit line. The row decoder group may be configured to simultaneously select the first half memory block and the second half memory block in response to a single block selection signal.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Eom
  • Hybrid non-volatile memory devices with static random access memory (SRAM) array and non-volatile memory (NVM) array
    Patent number: 10559344
    Abstract: Technologies are generally described herein for a hybrid non-volatile memory structure that includes a number of SRAM buffers. SRAM access times may be achieved for non-volatile read/write operations by performing access queue buffered read/write operations first. The SRAM buffer may be shareable as a system SRAM. In other examples, a hybrid non-volatile memory according to some embodiments may include a high speed block and a high endurance block to store different types of data with different access needs. The hybrid non-volatile memory may also include a normal block to store the data which is non-frequently changed.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: February 11, 2020
    Assignee: Aspiring Sky Co. Limited
    Inventors: Zhijiong Luo, Shu Wang, Xiaoming Jin
  • Memory system with signals on read lines not phase-aligned with Josephson transmission line (JTL) elements included in the write lines
    Patent number: 10541024
    Abstract: Current-based superconductor memory cell and related systems and methods are provided. A method in a memory system, having at least one storage circuit and at least one read SQUID, includes applying bit-line current, via a read bit-line not including any Josephson transmission line (JTL) elements, to the at least one read SQUID. The method further includes applying word-line current, via a read word-line not including any JTL elements, to the at least one read SQUID. The method further includes using the at least one read SQUID reading a logic state of the memory cell based on data maintained in the storage circuit.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Randall M. Burnett, Randal L. Posey, Haitao O. Dai, Quentin P. Herr
  • Semiconductor apparatus related to the repairing of a redundancy region
    Patent number: 10541045
    Abstract: A semiconductor apparatus includes a fuse array, a word line decoder, a bit line decoder, a bank information comparison circuit, and a rupture circuit. The word line decoder is configured to select a word line of the fuse array based on a bank select address signal. The bit line decoder is configured to select a bit line of the fuse array based on a fail row address signal. The bank information comparison circuit and the rupture circuit are configured to rupture a fuse coupled to the word line and the bit line when a fail bank address signal and the bank select address signal correspond to each other.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: January 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Keun Sik Ko
  • Integrated circuit memory device with write driver and method of operating same
    Patent number: 10535392
    Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: January 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Artur Antonyan
  • Memory chip, package device having the memory chips, and operating method of package device
    Patent number: 10529397
    Abstract: Provided herein may be a memory chip, a package device having the memory chip, and a method of operating the package device. The memory chip comprising a plurality of memory blocks each including a plurality of memory cells for storing data; a plurality of input/output pads to which a chip address is inputted; and a plurality of peripheral circuits configured to program the chip address to a selected memory block among the memory blocks.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Jin Yong Seong, Ho Jun Kang, Sang Bin Park
  • Semiconductor device providing an output in response to a read command or a mode-register read command
    Patent number: 10515683
    Abstract: Disclosed herein is an apparatus that includes a first circuit that activates first and second timing signals in response to a first command and activates the second timing signal in response to a second command, a second circuit that amplifies a first data read out from a first memory area in response to the first command in synchronization with the first timing signal, and a third circuit that outputs one of the first data output from the second circuit and a second data read out from a second memory area in response to the second command, in synchronization with the second timing signal.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Takayuki Miyamoto