Abstract: An integrated circuit structure includes an SRAM array including a first sub-array having a first plurality of rows and a plurality of columns of SRAM cells, and a second sub-array having a second plurality of rows and the plurality of columns of SRAM cells. A first bit-line and a first complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in a column in the first sub-array. A second bit-line and a second complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in the column in the second sub-array. The first bit-line and the first complementary bit-line are disconnected from the second bit-line and the second complementary bit-line. A sense amplifier circuit is electrically coupled to, and configured to sense, the first bit-line, the first complementary bit-line, the second bit-line, and the second complementary bit-line.

Abstract: Methods and apparatus are disclosed for operating a memory cell formed from the plurality of coupled Josephson junctions. The memory cell is configured such that applying an electrical signal to the junctions can cause at least one, but not all, of the junctions to change their respective phase states. Subsequent writes to the memory cell using substantially the same electrical pulse do not change the phase state of the plurality of junctions. The memory cell can be ready by providing another electrical pulse to one of the junctions and receiving an output electrical pulse generated in response by a different Josephson junction of the memory cell. A set of phase states are selected to represent the logic values that are stable across anticipated operating conditions for the memory cell. Methods of selecting electrical parameters and manufacturing memory cells are further disclosed.

Abstract: In the disclosure, a non-volatile memory device includes a resistive memory cell and a write and read circuit. The write and read circuit is coupled to the resistive memory cell and configured to combine a perturbation AC signal with a first writing signal, so as to generate a second writing signal. Then, the write and read circuit applies the second writing signal to the resistive memory cell to program the resistive memory cell. The combination of the oscillation signal and the first writing signal (constant DC signal) and AC signal would penetrate the shielding effect of the insulating layer and free the stuck charges.

Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a maintaining circuit, a sensing circuit, an output circuit, and a verification circuit. The maintaining circuit is configured to maintain data read from a memory cell array and output the data to a data bus in response to a column selection signal. The sensing circuit is configured to sense the data on the data bus in response to at least one sensing enable signal. The output circuit is configured to output the data sensed by the sensing circuit. The verification circuit is configured to verify an operation margin of the sensing circuit and output a verification result. The timing of the at least one sensing enable signal is set according to the verification result of the verification circuit.

Abstract: A data storage device includes a first memory device having a buffer region including a general region and a host access region, a second memory device, and a controller. The first memory device is directly accessible by the host. The controller controls the first memory device or the second memory device to store data provided from the host. The controller stores the data in the host access region and generates metadata of the data, when the data provided from the host complies with a predetermined condition.

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

Abstract: A Flash memory access module performs memory access management of a Flash storage device including a plurality of storage cells. The Flash memory access module includes: a read only memory for storing a program code; and a microprocessor which executes the program code to perform the following steps: performing a first sensing operation corresponding to a first sensing voltage in a storage cell, and performing a second sensing operation in the storage cell; using the first sensing operation and at least the second sensing operation to generate a first digital value and a second digital value, respectively, of the storage cell; using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.

Abstract: Systems and methods are provided, which facilitate operations planning, dispatch, regulation control, and autonomous control performance. The disclosure also facilitates systems and methods for utilization of synthetic primary frequency response, synthetic inertia, regulation and load following/ramping reserve capabilities from Demand Response and Distributed Energy Resources for balancing demand and supply and maintaining frequency levels across a power grid.

Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first and second magnetic layers, a first nonmagnetic layer and a controller. The conductive layer includes first and second portions, and a third portion between the first and second portions. The first magnetic layer is separated from the third portion in a first direction crossing a second direction being from the first portion toward the second portion. The second magnetic layer is provided between the first magnetic layer and at least a portion of the third portion. The first nonmagnetic layer includes first and second regions. The first region is provided between the first and second magnetic layers. The second region is continuous with the first region. The second region overlaps at least a portion of the second magnetic layer in the second direction. The controller is electrically connected to the first and second portions.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a non-volatile storage controller that identifies a threshold number of bit flips that can be corrected in an amount of read data and a memory die comprising a plurality of non-volatile memory cells. Here, the memory die receives the threshold number of bit flips from the non-volatile storage controller, programs data to a set of the non-volatile memory cells over a first number of program loop cycles, and programs the data to the set of non-volatile memory cells over an additional number of program loop cycles in response to the amount of bit flips in the set of memory cells exceeding the threshold number of bit flips.

Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.

Abstract: This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.

Abstract: A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.

Abstract: An apparatus has a reference magnetic tunnel junction with a high aspect ratio including a reference layer with magnetization along a minor axis and a storage layer with magnetization along a major axis. The storage layer magnetization is substantially perpendicular to the magnetization along the minor axis. The magnetization orientation between the minor axis and the major axis is maintained by shape anisotropy caused by the high aspect ratio.

Abstract: A nonvolatile memory device according to some embodiments of the inventive concepts may include a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second page buffer connected to the memory cell array via a second plurality of bit lines. The first page buffer circuit may include a first bit line selection circuit, a first bit line shut-off circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line shut-off circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line shut-off circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. A width of the data lines may be greater than a width of the bit lines.

Abstract: A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4F2 area. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.

Abstract: According to one general aspect, an apparatus may include a global bit line, and a plurality of memory banks. The global bit line may be configured to facilitate a memory access. Each memory bank may include a local keeper-precharge circuit coupled between a power supply and the global bit line, and a control circuit configured to control, at least in part, the local keeper-precharge circuit.

Abstract: A memory device includes a first fail address register that stores a fail address, an input address register that stores an input address, a data comparison circuit that compares write data to be stored in a memory cell corresponding to the input address with read data read from the memory cell, an address comparison circuit that compares the fail address and the input address, and a second fail address register that stores bits of the fail address in parallel based on a first comparison result of the write data with the read data and a second comparison result of the fail address with the input address.

Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.