Abstract: A method of manufacturing a display apparatus is provided. The method includes forming a test area on a display substrate, irradiating a first laser to the test area and determining relative positions of the test area and a first irradiation area formed by irradiating the first laser to the test area, and correcting a position of a second laser irradiated to the display substrate based on the relative positions of the test area and the first irradiation area.

Abstract: A display device includes a display panel. The display panel includes a pixel, an encapsulation layer, and a connection electrode connecting a signal line and a pad electrode. The encapsulation layer includes an outer region in which a first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact, and an inner region in which an organic encapsulation layer is disposed. A first connection electrode overlaps the outer region.

Abstract: A quantum device configured to be able to form an array of quantum dots, the device including for this: an active layer made of a semiconductor material; a plurality of first gates disposed along a plurality of rows; a plurality of second gates disposed along a plurality of columns perpendicular to the rows of the plurality of rows; a plurality of third gates, each third gate of the plurality of third gates being disposed at the intersection of one row of the plurality of rows and one column of the plurality of columns, each third gate being separated from the nearest third gates, on a row by a first gate and on a column by a second gate; the active layer including apertures over the entire thickness of the active layer disposed between the rows of the plurality of rows and the columns of the plurality of columns.

Abstract: The present disclosure provides a micro light-emitting element, method for manufacturing a micro light-emitting element, and a light-emitting device. The micro light-emitting element includes a DBR structure layer, including a DBR adhesive layer, a DBR reflective layer, and a DBR sacrificial layer, where the DBR adhesive layer, the DBR reflective layer, and the DBR sacrificial layer are sequentially stacked. Subsequent structural coverage of a DBR reflective layer is improved by means of the DBR adhesion layer. Density of film layers of the DBR sacrificial layer, the DBR reflective layer, and the DBR adhesive layer are sequentially increased, so that etching rates of the DBR sacrificial layer, the DBR reflective layer, and the DBR adhesive layer are sequentially decreased during etching, thereby forming an inverted trapezoidal through hole which comprises an inclined side wall by an etching process.

Abstract: Bipolar junction transistor (BJT) structures are provided. First and second well regions are formed over a dielectric layer. A plurality of first and second gate-all-around (GAA) field-effect transistors are formed over a first well region. A plurality of third GAA field-effect transistors are formed over the second well region. Source/drain features of the first and third GAA field-effect transistors and the second well region have a first conductivity type. Source/drain features of the second GAA field-effect transistors and the first well region have a second conductivity type that is different from the first conductivity type. A first PN junction of a first BJT device is formed between the source/drain features of the first GAA field-effect transistors and the first well region, and a second PN junction of the first BJT device is formed between the first well region and the second well region.

Abstract: An image sensor including a substrate having a pixel region, a floating diffusion region in the pixel region of the substrate, a plurality of photoelectric conversion regions around the floating diffusion region in the substrate, a plurality of transmission gates adjacent to the plurality of photoelectric conversion regions, respectively, each including a first buried gate extending to the inside of the substrate, a second buried gate apart from the first buried gate and extending to the inside of the substrate, and a gate connection between the first buried gate and the second buried gate, and a plurality of spacers each on at least parts of side walls of each of the plurality of transmission gates, wherein each of the plurality of spacers is between the side walls of each of the plurality of transmission gates and the floating diffusion region in a plan view.

Abstract: A chip packaging structure is provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, a grating film, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate and has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The second substrate is disposed on an upper surface of the supporting member. The grating film is disposed on a peripheral region of the second substrate and includes a plurality of grating units. The encapsulant is attached to the upper surface of the first substrate, a side surface of the supporting member, and a side surface of the second substrate.

Abstract: A lead frame has a back surface having a multiple-irradiated region that is irradiated with laser light scanned in a first scan step and laser light scanned in a second scan step, a unit resin molded product that is formed in a cutting step has corner regions overlapping the multiple-irradiated region of the lead frame, and the multiple-irradiated region prevents the laser light emitted to the back surface from reaching portions of the resin material on the front surface of the lead frame, the portions being located at a position corresponding to the corner regions.

Abstract: A thin film transistor and an ultrasonic imaging base board. The thin film transistor includes: a substrate (100), and a first gate (101), a first gate insulation layer (102), a first active layer (103), a second gate insulation layer (104) and a second gate (105) stacked on a side of the substrate (100), and the first gate (101) is connected to the second gate (105).

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a first nitride region, and a first insulating member. The first semiconductor region includes Alx1Ga1-x1N (0?x1<1). The second semiconductor region includes Alx2Ga1-x2N (0<x2<1, x1<x2). A first nitride portion thickness along a second direction of the first nitride portion is thicker than a second nitride portion thickness along the first direction of the part of the second nitride portion. A first semiconductor portion thickness along the second direction of the first semiconductor portion is thicker than the first nitride portion thickness.

Abstract: A stack package is provided. The stack package includes a package substrate on which a first bond finger and a second bond finger are spaced apart from each other, and a second semiconductor die stacked over a first semiconductor die. A first connector connects the first semiconductor die to the first bond finger. A second connector connects the second semiconductor die to the second bond finger and extends to have substantially the same length as the first connector.

Abstract: A display device that has high display quality is provided. A highly reliable display device is provided. A display device with low power consumption is provided and a display device that can easily achieve a higher resolution is provided. A display device with both high display quality and a high resolution is provided. A display device with high contrast is provided. The display device includes a first layer, a second layer over the first layer, and a third layer over the second layer. The first layer includes a first transistor including silicon in a channel formation region. The second layer includes a second transistor including a metal oxide in a channel formation region.

Abstract: A light-emitting device includes a first electrode, a second electrode, a light-emitting layer disposed between the first electrode and the second electrode, and a carrier functional layer disposed between the first electrode and the light-emitting layer. The carrier functional layer includes a first carrier functional layer and a second carrier functional layer, the first carrier functional layer is closer to the light-emitting layer than the second carrier functional layer, the first carrier functional layer contains a host material and a ligand material, the second carrier functional layer contains a host material, and the host material of the first carrier functional layer and the host material of the second carrier functional layer include same atoms. A mass fraction of the ligand material of the first carrier functional layer is greater than a mass fraction of a ligand material of the second carrier functional layer.

Abstract: A Group-III element nitride semiconductor substrate includes: a first surface; and a second surface, wherein warping of a crystal plane of the first surface has a plurality of extremes.

Abstract: A display device includes a substrate having an active area including a plurality of pixels and a non-active area surrounding the active area; an inorganic insulating layer on the substrate and extending from the active area to the non-active area; a gate in panel (GIP) driving circuit in the non-active area and applying a gate signal to each of the plurality of sub pixels in the active area; a plurality of gate link lines which transmits a gate driving signal transmitted from the outside to the GIP driving circuit; a plurality of low potential voltage lines which transmits a low potential voltage to the GIP driving circuit; and at least one of first heat transfer prevention patterns disposed in an area in which the low potential voltage is applied from the plurality of low potential voltage lines to the GIP driving circuit.

Abstract: A display substrate comprises a display area and a bezel area, wherein a side of the display area close to the bezel area forms a first step-shaped display area boundary, the bezel area at least comprises a capacitance area, the capacitance area comprises a plurality of compensation capacitors, and the plurality of compensation capacitors form a second step-shaped capacitance area boundary on a side far away from the display area; the display area boundary comprises a plurality of first steps connected in sequence, the first steps having a first step length and a first step width, and the capacitance area boundary comprises a plurality of second steps connected in sequence.

Abstract: A method for manufacturing a growth substrate, including producing mesas based on GaN having various porosification levels, implementing differentiated steps of electrochemical porosification, non-photoassisted and photoassisted, of various portions of the mesas.

Abstract: Provided is a light receiving element capable of improving a transfer failure in a structure in which a photoelectric converter is embedded. A light receiving element includes a photoelectric conversion region of a first conductivity type, a well region of a second conductivity type provided on a side of one surface of the photoelectric conversion region, a floating diffusion region of the first conductivity type provided on a side of a one surface of the well region opposite to the photoelectric conversion region, a transfer gate electrode that is embedded in a depth direction of the well region with a gate insulating film interposed therebetween and transfers a signal charge photoelectrically converted in the photoelectric conversion region to the floating diffusion region, and an auxiliary electrode that is embedded in the well region with the gate insulating film interposed therebetween and extends toward a side surface of the transfer gate electrode.

Abstract: A capacitor structure includes a lower electrode structure disposed on a substrate, including an oxide of a first metal having 4 valence electrons, and being doped with a second metal having 3, 5, 6, or 7 valence electrons, a dielectric pattern disposed on a sidewall of the lower electrode structure, and an upper electrode disposed on a sidewall of the dielectric pattern.

Abstract: An electronic device is provided and includes a circuit substrate and a light emitting chip. The light emitting chip is disposed on the circuit substrate, and the light emitting chip includes a first light emitting diode and a second light emitting diode electrically connected to each other. The first light emitting diode has a first light distribution curve, the second light emitting diode has a second light distribution curve, and the first light distribution curve is different from the second light distribution curve.