Patents Examined by David Vu
  • Patent number: 11367623
    Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Patent number: 11362170
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a second electrode layer formed over the first electrode layer, and a second spacer formed on a sidewall of the second electrode layer. The second spacer is in direct contact with an interface between the second electrode layer and a first dielectric layer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Fan Huang, Chih-Yang Pai, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11362192
    Abstract: A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 14, 2022
    Assignees: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD., JIANGSU ADVANCED MEMORY SEMICONDUCTOR CO., LTD.
    Inventors: Chieh-Fang Chen, Kuo-Feng Lo, Chung-Hon Lam, Yu Zhu
  • Patent number: 11362082
    Abstract: A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Paul Fischer, Walid Hafez, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11362117
    Abstract: The present application provides a method of manufacturing an array substrate, the array substrate, and a display device. In the method, a photoresist layer is removed by a plasma cleaning technique after performing etching to prevent a gate electrode of the array substrate from contacting a stripping solution, thereby preventing a metal layer of the gate electrode from being corroded by the stripping solution.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 14, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Tian Ou
  • Patent number: 11355540
    Abstract: An optical device includes a first conductive layer, a first junction layer, a light absorption layer, a second junction layer, and a second conductive layer. The first junction layer is disposed on the first conductive layer. The light absorption layer is disposed on the first junction layer, wherein the light absorption layer includes a plurality of unit cells, each of the unit cells includes a plurality of pillar structures, and the pillar structures of each of the unit cells are different sizes. The second junction layer is disposed on the light absorption layer. The second conductive layer is disposed on the second junction layer.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: June 7, 2022
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Kuo-Feng Lin, Chin-Chuan Hsieh
  • Patent number: 11355704
    Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: June 7, 2022
    Assignee: Tsinghua University
    Inventors: Huaqiang Wu, Wei Wu, Bin Gao, He Qian
  • Patent number: 11355598
    Abstract: A semiconductor device having a back-side field plate includes a buffer layer that includes a first compound semiconductor material, where the buffer layer is epitaxial to a crystalline substrate. The semiconductor device also includes field plate layer that is disposed on a surface of the buffer layer. The semiconductor device further includes a first channel layer disposed over the field plate layer, where the first channel layer includes the first compound semiconductor material. The semiconductor device further includes a region comprising a two-dimensional electron gas, where the two-dimensional electron gas is formed at an interface between the first channel layer and a second channel layer. The semiconductor device additionally includes a back-side field plate that is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: June 7, 2022
    Assignee: Analog Devices, Inc.
    Inventors: Puneet Srivastava, James G. Fiorenza, Daniel Piedra
  • Patent number: 11355725
    Abstract: A composite thin film includes N thin film layers stacked one over another in sequence from a first thin film layer to an N-th thin film layer. N is an integer satisfying 3?N?9. The N thin film layers are nano-ZnO thin films. A nano-ZnO particle size of the nano-ZnO thin films gradually increases or decreases from the first thin film layer to the N-th thin film layer.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: June 7, 2022
    Assignee: TCL TECHNOLOGY GROUP CORPORATION
    Inventor: Longjia Wu
  • Patent number: 11348786
    Abstract: The superior electronic and mechanical properties of 2D-layered transition metal dichalcogenides and other 2D layered materials could be exploited to make a broad range of devices with attractive functionalities. However, the nanofabrication of such layered-material-based devices still needs resist-based lithography and plasma etching processes for patterning layered materials into functional device features. Such patterning processes lead to unavoidable contaminations, to which the transport characteristics of atomically-thin layered materials are very sensitive. More seriously, such lithography-introduced contaminants cannot be safely eliminated by conventional material wafer cleaning approaches. This disclosure introduces a rubbing-induced site-selective growth method capable of directly generating few-layer molybdenum disulfide device patterns without the need of any additional patterning processes.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 31, 2022
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Xiaogan Liang, Byunghoon Ryu
  • Patent number: 11348805
    Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: May 31, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
  • Patent number: 11342186
    Abstract: A semiconductor device wherein a hydrogen concentration distribution has a first hydrogen concentration peak and a second hydrogen concentration peak and a donor concentration distribution has a first donor concentration peak and a second donor concentration peak in a depth direction, wherein the first hydrogen concentration peak and the first donor concentration peak are placed at a first depth and the second hydrogen concentration peak and the second donor concentration peak are placed at a second depth deeper than the first depth relative to the lower surface is provided.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 24, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasunori Agata, Takashi Yoshimura, Hiroshi Takishita, Misaki Meguro, Naoko Kodama, Yoshihiro Ikura, Seiji Noguchi, Yuichi Harada, Yosuke Sakurai
  • Patent number: 11342242
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 11335692
    Abstract: The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 17, 2022
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT MFG. CO., LTD.
    Inventors: Qiwei Wang, Jinshuang Zhang, Haoyu Chen, Rong Zou, Juanjuan Li
  • Patent number: 11335775
    Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Srinivas Pulugurtha, Jaydip Guha, Scott E. Sills, Yi Fang Lee
  • Patent number: 11333946
    Abstract: The present invention provides a display panel and a display module. The display panel comprises at least two pixel units. Each pixel units comprises a substrate, a thin film transistor (TFT) disposed on the substrate, and a pixel electrode disposed on the thin film transistor. The thin film transistor and the pixel electrode disposed in the same pixel unit are insulated from each other. The thin film transistor disposed in the pixel unit is electrically connected to a pixel electrode disposed in another pixel unit, which is disposed parallel to the pixel unit.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: May 17, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wu Cao
  • Patent number: 11335789
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Cory Weber, Van H. Le, Sean Ma
  • Patent number: 11329104
    Abstract: A display panel and a display device are provided. The display panel includes a substrate layer, a light emitting layer, a package layer, a filter layer and an organic flat layer. The organic flat layer covers the filter layer. The light emitting layer further includes a pixel area and a pixel interval area. The filter layer further includes an R/G/B filter area and a layer stacked area. The layer stacked area is a stacked structure of R/G/B three-layer filter layers. The layer stacked structure can thin the thickness of the display panel and improve the flexibility of the display panel.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 10, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liang Sun, Mian Zeng
  • Patent number: 11329159
    Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, Ka-Hing Fung, Li-Ping Huang, Wei-Yuan Lu
  • Patent number: 11322497
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: May 3, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Yves T. Ngu, Ephrem G. Gebreselasie, Vibhor Jain, Johnatan A. Kantarovsky