Patents Examined by David Vu
  • Patent number: 10347558
    Abstract: Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 9, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Christian Geissler, Georg Seidemann, Sonja Koller, Jan Proschwitz
  • Patent number: 10347594
    Abstract: A semiconductor device includes a wiring, a semiconductor chip above the wiring and a metal block above the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a lower electrode, an upper large electrode and an upper small electrode. The semiconductor chip includes a first portion and a second portion, the first portion being on an upper small electrode side with respect to a centroid of the semiconductor chip, the second portion being on an opposite side of the upper small electrode with respect to the centroid. The lower electrode is connected to the wiring via a lower solder layer. The lower solder layer includes a solder base material and metal particles. A volume ratio of the metal particles occupying the lower solder layer under the second portion is higher than a volume ratio of the metal particles occupying the lower solder layer under the first portion.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 9, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masayuki Kamiya
  • Patent number: 10345639
    Abstract: A curved display includes a first substrate and a second substrate in a stacked configuration. The first substrate includes pixel electrodes that are arranged in a matrix and electrical lines that extend in a first direction. The second substrate includes light shielding portions that extend in the first direction. Also disclosed is a method for manufacturing a curved display that includes attaching a first substrate to a second substrate in a stacked configuration and bending the first substrate and the second substrate to be curved.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 9, 2019
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventor: Teruhisa Nakagawa
  • Patent number: 10347683
    Abstract: A photo detector device is provided. The photo detector device includes a substrate, a first metal layer, a first interlayer dielectric layer, an active layer, a photodiode, and a second metal layer. The first metal layer is disposed on the substrate, wherein the first metal layer includes a gate line and a gate, and the gate is electrically connected to the gate line. The first interlayer dielectric layer is disposed on the first metal layer. The active layer is electrically insulated from the gate and partially overlaps the gate. The photodiode is disposed on the substrate. The second metal layer is disposed on the first interlayer dielectric layer, wherein the second metal layer includes a data line and a bias line, and the bias line is disposed on the photodiode.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: July 9, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Yu-Tsung Liu, Te-Yu Lee
  • Patent number: 10339446
    Abstract: A neuromorphic device may include: a plurality of row lines extending in a first direction; a plurality of additional row lines extending in the first direction; a plurality of column lines extending in a second direction that crosses the first direction; and a plurality of synapses positioned at intersections of the row lines, the additional row lines, and the column lines, wherein each of the synapses includes a transistor comprising a floating gate, a control gate insulated from the floating gate, a first junction, and a second junction, the control gate being coupled to a corresponding one of the plurality of row lines, the first junction being coupled to a corresponding one of the plurality of additional row lines, the second junction being coupled to a corresponding one of the plurality of column lines.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: July 2, 2019
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Patent number: 10340145
    Abstract: An integrated circuit element and a fabrication method thereof, a circuit board, a display panel and a display device are provided, to reduce space occupied by the integrated circuit element and facilitate achieving intelligent transparent display by arranging the integrated circuit element in a display. The integrated circuit element includes a base plate, and a bare integrated circuit chip and multiple connection parts arranged on the base plate. The bare integrated circuit chip includes multiple connection points that are respectively electrically connected to the multiple connection parts.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 2, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yuzhen Guo, Xue Dong, Haisheng Wang, Chunwei Wu, Yingming Liu, Xiaoliang Ding, Rui Xu, Changfeng Li, Lijun Zhao, Yanling Han, Pengpeng Wang, Xueyou Cao, Ping Zhang, Wei Liu, Yanan Jia
  • Patent number: 10340378
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, an interconnect portion, and a second electrode. The gate electrode includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first portion opposes the first to third semiconductor regions. The second portion is separated from the first portion. The fourth semiconductor region includes a first region opposing the second portion. The interconnect portion is electrically connected to the third portion. The second electrode is provided on the second and third semiconductor regions and the first region. The second electrode is electrically connected to the second to fourth semiconductor regions.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 2, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Masatoshi Arai
  • Patent number: 10340261
    Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays, and a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits. The first and second semiconductor chips are stacked with each other so that each of the first bonding electrodes is electrically connected to an associated one of the second bonding electrodes.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Mitsunari Sukekawa
  • Patent number: 10332851
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: June 25, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chung-Chieh Yang, Sheng-Ming Wang, Tien-Szu Chen
  • Patent number: 10332963
    Abstract: Methods of forming a structure for a field-effect transistor and related structures. A trench is formed in one or more semiconductor layers, and forming first and second sacrificial sidewall spacers are formed on an upper portion of the trench. A material is formed in the trench that is arranged in part between the first sacrificial sidewall spacer and the second sacrificial space. After forming the material in the trench, the first and second sacrificial sidewall spacers are removed. After removing the first and second sacrificial sidewall spacers, an upper portion of the material is removed with an isotropic etching process.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ruilong Xie
  • Patent number: 10322930
    Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chung-Yen Chou, Lee-Chuan Tseng, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10325918
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 10319631
    Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: June 11, 2019
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 10319640
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10319941
    Abstract: An organic EL display device (electroluminescence device) including a TFT substrate (substrate), an organic EL element (electroluminescence element) disposed on the TFT substrate, a first inorganic film covering the organic EL element, at least one protruding body having a frame shape, the at least one protruding body being configured by an organic film and surrounding the electroluminescence element on the first inorganic film, a second inorganic film covering the first inorganic film and the at least one protruding body, and a leveled film configured by an organic film and provided on the second inorganic film.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: June 11, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Hirase, Tetsuya Okamoto, Tohru Senoo, Tohru Sonoda, Mamoru Ishida
  • Patent number: 10312205
    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface, the active surface having a connection pad disposed thereon, and an inactive surface opposing the active surface; an encapsulant encapsulating at least a portion of the semiconductor chip; an insulating layer disposed on the active surface of the semiconductor chip; and a redistribution layer disposed on the insulating layer and electrically connected to the connection pad. The insulating layer includes a low tan delta (Df) dielectric material.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: June 4, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Youn Gyu Han
  • Patent number: 10312257
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 4, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Akio Kaneko
  • Patent number: 10312251
    Abstract: A semiconductor memory device according to an embodiment includes a stacked body in which an electrode film and an insulating film are alternately stacked along a first direction, a semiconductor member extending in the first direction and piercing the stacked body, and a charge storage member provided between the semiconductor member and the electrode film. The electrode film includes a first portion. The first portion is composed of a metal silicide. The first portion surrounds the semiconductor member as viewed from the first direction.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 4, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Sonehara
  • Patent number: 10312414
    Abstract: A light emitting unit and a display device is disclosed, wherein the display device includes: a light emitting unit, including: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a first protecting layer disposed on the second semiconductor layer, wherein the first protecting layer includes oxygen, nitrogen, and at least one element selected from the group consisting of Al, Ga, In, and Si.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 4, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Jia-Yuan Chen, Kuan-Feng Lee, Tsung-Han Tsai, Hsiao-Lang Lin, Jui-Jen Yueh
  • Patent number: 10304943
    Abstract: An integrated circuit device may include a gate dielectric layer on an inner surface of a gate trench of a substrate, a gate structure filling a portion of the gate trench on the gate dielectric layer, and an insulating, capping pattern on an upper surface of the gate structure in the gate trench. The gate structure may include a lower gate line having a first work function, an upper gate line having a second work function lower than the first work function, a first blocking layer between the lower gate line and the upper gate line, and a second blocking layer between the upper gate line and the insulating capping pattern.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hyun Lee, Jun-sik Kim, Kyo-suk Chae