Abstract: The invention relates to an optoelectronic semiconductor layer sequence comprising:—an active layer for generating radiation, and—at least one filter layer configured to at least partially absorb the electromagnetic radiation generated by the active layer of wavelengths smaller than a predetermined cutoff wavelength. The invention also relates to an optoelectronic semiconductor device.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a dielectric spacer layer underlying the alternating stack, memory opening vertically extending through the alternating stack, and through the dielectric spacer layer, a memory opening fill structure located in the memory opening and including a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film, and a source layer located under the dielectric spacer layer and contacting the pillar portion of the vertical semiconductor channel.

Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode, a magnetic tunnel junction (MTJ) and a top electrode disposed on the MTJ. The MTJ has a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. The bottom electrode and the top electrode are recessed within a periphery of the MTJ to form a disrupted sidewall profile.

Abstract: A semiconductor structure including a semiconductor die, a component layer and a pseudo static random access memory (PSRAM) die is provided. The component layer is disposed on the surface of the semiconductor die, wherein the component layer includes an organic layer. The PSRAM die is disposed on the surface of the semiconductor die and is electrically connected to the semiconductor die. A manufacturing method of a semiconductor structure is also provided.

Abstract: A semiconductor device includes a stacked body including stacked insulating layers and stacked conductive layers; a cell plug; a connection contact structure; and a source layer coupled to the cell plug. The cell plug includes upper and lower portions, the connection contact structure includes a first connection contact disposed at substantially the same level as the lower portion of the cell plug, and a second connection contact disposed at substantially the same level as the upper portion thereof, a level at which the first and second connection contacts contact each other is substantially the same as a level at which the upper and lower portions of the cell plug contact each other, and a level of an uppermost portion of the second connection contact is higher than a level of a bottom surface of the source layer, and is lower than a level of a top surface thereof.

Abstract: An image sensor includes a substrate having an element separation pattern, a first active region, and a ground region, the ground region being separated from the first active region by the element separation pattern, a transfer transistor including a transfer gate electrode on the first active region, the transfer gate electrode being separated from the ground region by the element separation pattern, a photo diode within the substrate, the photo diode being spaced apart from the transfer gate electrode, and a contact on the ground region, the contact being configured to receive a ground voltage.

Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stack, a pass gate overlapping a contact region of the gate stack and opening a cell array region of the gate stack, a doped semiconductor layer spaced apart from the pass gate and overlapping the cell array region of the gate stack, and an active pillar passing through the pass gate.

Abstract: A semiconductor device includes a trench formed in an element formation region of a semiconductor substrate, an insulating film formed on an inner wall of the trench, a p-type semiconductor portion embedded in a part of the trench via the insulating film, and an n-type semiconductor portion embedded in another part of the trench via the insulating film and provided so as to contact with the p-type semiconductor portion.

Abstract: A method of manufacturing a display apparatus is provided. The method includes forming a test area on a display substrate, irradiating a first laser to the test area and determining relative positions of the test area and a first irradiation area formed by irradiating the first laser to the test area, and correcting a position of a second laser irradiated to the display substrate based on the relative positions of the test area and the first irradiation area.

Abstract: A display device includes a display panel. The display panel includes a pixel, an encapsulation layer, and a connection electrode connecting a signal line and a pad electrode. The encapsulation layer includes an outer region in which a first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact, and an inner region in which an organic encapsulation layer is disposed. A first connection electrode overlaps the outer region.

Abstract: A quantum device configured to be able to form an array of quantum dots, the device including for this: an active layer made of a semiconductor material; a plurality of first gates disposed along a plurality of rows; a plurality of second gates disposed along a plurality of columns perpendicular to the rows of the plurality of rows; a plurality of third gates, each third gate of the plurality of third gates being disposed at the intersection of one row of the plurality of rows and one column of the plurality of columns, each third gate being separated from the nearest third gates, on a row by a first gate and on a column by a second gate; the active layer including apertures over the entire thickness of the active layer disposed between the rows of the plurality of rows and the columns of the plurality of columns.

Abstract: The present disclosure provides a micro light-emitting element, method for manufacturing a micro light-emitting element, and a light-emitting device. The micro light-emitting element includes a DBR structure layer, including a DBR adhesive layer, a DBR reflective layer, and a DBR sacrificial layer, where the DBR adhesive layer, the DBR reflective layer, and the DBR sacrificial layer are sequentially stacked. Subsequent structural coverage of a DBR reflective layer is improved by means of the DBR adhesion layer. Density of film layers of the DBR sacrificial layer, the DBR reflective layer, and the DBR adhesive layer are sequentially increased, so that etching rates of the DBR sacrificial layer, the DBR reflective layer, and the DBR adhesive layer are sequentially decreased during etching, thereby forming an inverted trapezoidal through hole which comprises an inclined side wall by an etching process.

Abstract: Bipolar junction transistor (BJT) structures are provided. First and second well regions are formed over a dielectric layer. A plurality of first and second gate-all-around (GAA) field-effect transistors are formed over a first well region. A plurality of third GAA field-effect transistors are formed over the second well region. Source/drain features of the first and third GAA field-effect transistors and the second well region have a first conductivity type. Source/drain features of the second GAA field-effect transistors and the first well region have a second conductivity type that is different from the first conductivity type. A first PN junction of a first BJT device is formed between the source/drain features of the first GAA field-effect transistors and the first well region, and a second PN junction of the first BJT device is formed between the first well region and the second well region.

Abstract: An image sensor including a substrate having a pixel region, a floating diffusion region in the pixel region of the substrate, a plurality of photoelectric conversion regions around the floating diffusion region in the substrate, a plurality of transmission gates adjacent to the plurality of photoelectric conversion regions, respectively, each including a first buried gate extending to the inside of the substrate, a second buried gate apart from the first buried gate and extending to the inside of the substrate, and a gate connection between the first buried gate and the second buried gate, and a plurality of spacers each on at least parts of side walls of each of the plurality of transmission gates, wherein each of the plurality of spacers is between the side walls of each of the plurality of transmission gates and the floating diffusion region in a plan view.

Abstract: A chip packaging structure is provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, a grating film, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate and has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The second substrate is disposed on an upper surface of the supporting member. The grating film is disposed on a peripheral region of the second substrate and includes a plurality of grating units. The encapsulant is attached to the upper surface of the first substrate, a side surface of the supporting member, and a side surface of the second substrate.

Abstract: A lead frame has a back surface having a multiple-irradiated region that is irradiated with laser light scanned in a first scan step and laser light scanned in a second scan step, a unit resin molded product that is formed in a cutting step has corner regions overlapping the multiple-irradiated region of the lead frame, and the multiple-irradiated region prevents the laser light emitted to the back surface from reaching portions of the resin material on the front surface of the lead frame, the portions being located at a position corresponding to the corner regions.

Abstract: A thin film transistor and an ultrasonic imaging base board. The thin film transistor includes: a substrate (100), and a first gate (101), a first gate insulation layer (102), a first active layer (103), a second gate insulation layer (104) and a second gate (105) stacked on a side of the substrate (100), and the first gate (101) is connected to the second gate (105).

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a first nitride region, and a first insulating member. The first semiconductor region includes Alx1Ga1-x1N (0?x1<1). The second semiconductor region includes Alx2Ga1-x2N (0<x2<1, x1<x2). A first nitride portion thickness along a second direction of the first nitride portion is thicker than a second nitride portion thickness along the first direction of the part of the second nitride portion. A first semiconductor portion thickness along the second direction of the first semiconductor portion is thicker than the first nitride portion thickness.

Abstract: A stack package is provided. The stack package includes a package substrate on which a first bond finger and a second bond finger are spaced apart from each other, and a second semiconductor die stacked over a first semiconductor die. A first connector connects the first semiconductor die to the first bond finger. A second connector connects the second semiconductor die to the second bond finger and extends to have substantially the same length as the first connector.

Abstract: A display device that has high display quality is provided. A highly reliable display device is provided. A display device with low power consumption is provided and a display device that can easily achieve a higher resolution is provided. A display device with both high display quality and a high resolution is provided. A display device with high contrast is provided. The display device includes a first layer, a second layer over the first layer, and a third layer over the second layer. The first layer includes a first transistor including silicon in a channel formation region. The second layer includes a second transistor including a metal oxide in a channel formation region.