Abstract: A photo transistor and a display device employing the photo transistor are provided. The photo transistor includes a gate electrode disposed on a substrate, a gate insulating layer that electrically insulates the gate electrode, a first active layer overlapping the gate electrode and including metal oxide, wherein the gate insulating layer is disposed between the gate electrode and the active layer, a second active layer disposed on the first active layer and including selenium, and a source electrode and a drain electrode respectively electrically connected to the second active layer.

Abstract: An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.

Abstract: There are provided methods of growing arrays of light emitters on substrates. An example method includes adjusting a growth parameter of a given light emitter of an array of light emitters on a substrate to obtain an adjusted growth parameter. The adjusting may be based on a location of the given light emitter on the substrate. The adjusting may be to compensate for nonuniformity in a growth profile of the light emitters across the substrate. The nonuniformity may be associated with a corresponding nonuniformity among wavelengths of light generated by the light emitters. Adjusting the growth parameter may be to adjust the corresponding nonuniformity. The method may also include growing the given light emitter on the substrate based on the adjusted growth parameter. Arrays of corresponding light emitters are also described.

Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

Abstract: In a described example, an apparatus includes: a photon detector array with a first signal output pad coupled to a photon detector array pixel; a die carrier comprising a readout integrated circuit (ROIC) die and a conductor layer having conductors that couple a first signal input pad on the conductor layer to an input signal lead of the ROIC die; and the first signal output pad coupled to the first signal input pad.

Abstract: A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.

Abstract: Some embodiments include an integrated assembly having a row of conductive posts. The conductive posts are spaced from one another by gaps. Leaker device material extends is within at least some of the gaps. An insulative material is along sidewalls of the conductive posts. A conductive structure is over the conductive posts. The conductive structure has downward projections extending into at least some of the gaps. The leaker device material is configured as segments along sides of the downward projections and extends from the sides to one or more of the conductive posts. Some embodiments include methods of forming integrated assemblies.

Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.

Abstract: An integrated circuit according to some example embodiments of inventive concepts includes a substrate including a well including dopants of a first conductivity type, a first device region on the well, the first device region extending in a first direction parallel to the substrate, and a first isolation element inside the well, the first isolation element extending in the first direction. The first isolation element includes a first power rail configured to receive a power source voltage, and a first doping region between the first power rail and the well, the first doping region configured to transfer the power source voltage from the first power rail to the well, and including dopants of the first conductivity type.

Abstract: A flexible array substrate, a manufacturing method thereof and a display device are provided. The flexible array substrate includes: a first flexible substrate with a first surface; a thin film transistor on the first surface; and a light-shielding layer between the first flexible substrate and the thin film transistor. An orthographic projection of the light-shielding layer on the first flexible substrate covers an orthographic projection of a channel region of the thin film transistor on the first flexible substrate.

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.

Abstract: An integrated circuit is described herein that includes a semiconductor substrate. First and second piezoresistive sensors are on or in the substrate where each have a respective sensing axis extending in first and second directions respectively parallel with a surface of the substrate, where the second direction is perpendicular to the first direction. A third piezoresistive sensor is on or in the substrate and has a respective sensing axis extending in a third direction parallel with the surface of the substrate and neither parallel nor perpendicular to the first and second directions.

Abstract: A memory device including a plurality of first conductive lines arranged on a substrate and spaced apart from each other in a first direction parallel to a top surface of the substrate; a plurality of capping liners on sidewalls of each of the plurality of first conductive lines, the plurality of capping liners having top surfaces at a vertical level equal to top surfaces of the plurality of first conductive lines, and bottom surfaces at a vertical level higher than bottom surfaces of the plurality of first conductive lines; and an insulating layer on the substrate, the insulating layer filling spaces between the plurality of first conductive lines and covering sidewalls of the plurality of capping liners.

Abstract: A display device includes pixel circuits disposed on a substrate, each of the pixel circuits comprising a transistor and a storage capacitor, display elements electrically connected to the pixel circuits, and a metal layer disposed between the substrate and the pixel circuits, the metal layer comprising through-holes, wherein the through-holes of the metal layer include a first through-hole, and a second through-hole disposed adjacent to the first through-hole.

Abstract: A semiconductor device includes first and second gate electrodes, a semiconductor layer between the first and second gate electrodes and extending along a first direction, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer between the second gate electrode and the semiconductor layer, a first insulating layer including a first region adjacent to the first gate electrode in the first direction and contacting the semiconductor layer, and a second insulating layer extending including a second region adjacent to the second gate electrode in the first direction and contacting the semiconductor layer. An interface between the first region and the semiconductor layer in a direction crossing the first direction is adjacent to the first gate electrode in the first direction.

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

Abstract: A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.