Abstract: In a semiconductor device, a protective film is disposed above a first surface of a semiconductor substrate. A first main electrode is disposed on the first surface of the semiconductor substrate and has an exposed portion exposed from an opening of the protective film. A second main electrode is disposed on a second surface of the semiconductor substrate. The semiconductor substrate includes an active region formed with IGBTs and diodes connected in antiparallel, as vertical elements. The opening of the protective film corresponds to the active region in a thickness direction. The active region includes an overlapping region overlapping with the exposed portion of the first main electrode, and a non-overlapping region without overlapping with the exposed portion in the thickness direction. A proportion of a diode-formed region in the non-overlapping region is higher than a proportion of a diode-formed region in the overlapping region.

Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) stack and a capping layer on the MTJ stack. The MTJ stack includes a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer. The capping layer includes a metal under layer that is in direct contact with the free layer, an oxide capping layer on the metal under layer, and a metal protection layer on the oxide capping layer.

Abstract: A field effect transistor includes a source region and a drain region embedded in a portion of a semiconductor substrate; a gate dielectric overlying a channel region located between the source region and the drain region; a gate electrode overlying the gate dielectric; a dielectric gate liner laterally surrounding the gate electrode; a inner gate spacer laterally surrounding the dielectric gate liner; a contoured gate capping dielectric including a vertically-extending portion that laterally surrounds the inner gate spacer and a horizontally-extending portion that overlies the gate electrode; and a outer gate spacer laterally surrounding the contoured gate capping dielectric.

Abstract: A coupon wafer for a micro-transfer printing process. The coupon wafer including a device coupon attached to a substrate of the coupon wafer by one or more tethers; wherein the or each tether is a pillar extending at least partially through the device coupon to contact the substrate of the coupon wafer.

Abstract: A display device includes: a through hole provided through a resin layer and all layers that are provided as overlying and underlying layers of the resin layer; and a non-display area including, in an extension of at least one of a plurality of inorganic insulating films from a display area and at least partway through a thickness of the resin layer, a slit formed so as to surround at least a part of the through hole, wherein the slit has two opposing side faces at least either one of which has an upper portion including the at least one of the plurality of inorganic insulating films, and the at least one of the plurality of inorganic insulating films that is shaped like an eave is, in the slit, in direct contact with a first inorganic sealing film covering the display area and the non-display area including the slit.

Abstract: A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.

Abstract: A semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface, which is located at substantially the same level as a top surface of the first etch stop layer.

Abstract: A method for fabricating a semiconductor memory device may include the steps of: forming a stacked body on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel holes through the stacked body, the channel holes each having a lower end extended into the source layer; forming a channel layer along the surfaces of the channel holes, the channel layer including a first region formed in the stacked body and a second region formed in the source layer; and forming a channel passivation layer in the first region to scale down the thickness of the channel layer of the first region.

Abstract: A chip package structure includes a substrate, a chip, a light-permeable element, a first anti-reflective layer, and an adhesive element. The chip is disposed on the substrate. The light-permeable element is disposed above the chip. The light-permeable element has a first surface and a second surface opposite to each other, and the first surface faces the chip. The first anti-reflective layer covers at least part of the first surface. The adhesive element is connected between the chip and the light-permeable element, and the adhesive element separates the chip and the light-permeable element. The adhesive element and the first anti-reflective layer are not in contact with each other.

Abstract: Provided is a gas sensor that can suppress characteristic variation caused by deformation of a semiconductor substrate. The gas sensor (1) includes a substrate (redistribution layer 30), a light-emitting element (11) provided at a front surface (30a) or embedded in the substrate, a light-receiving element (12) that is provided at the front surface or embedded in the substrate and that receives light emitted from the light-emitting element, and a plurality of external connection terminals (40) at a rear surface (30b) that is an opposite surface to the front surface of the substrate. At least a portion of the plurality of external connection terminals is electrically connected to the light-emitting element and the light-receiving element. The plurality of external connection terminals is arranged such that, in plan view, the light-emitting element and the light-receiving element are not present on a line linking any two external connection terminals.

Abstract: A method for fabricating a semiconductor device includes: forming a stack body including first sacrificial layer structures, preliminary horizontal layers, and second sacrificial layer structures over a lower structure; forming a main hard mask layer over the stack body; forming a mesh-shaped hard mask pattern over the main hard mask layer; forming a main hard mask pattern by etching the main hard mask layer using the mesh-shaped hard mask pattern as an etch barrier; forming a plurality of isolation openings by etching the stack body using the main hard mask pattern as an etch barrier; and forming a plurality of isolation layers that fill the isolation openings.

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

Abstract: A semiconductor packaging structure includes an encapsulation layer, a die, a first metal layer, a second metal layer and an electrical connection component. The die is disposed in the encapsulation layer. The first metal layer and the second metal layer are disposed in the encapsulation layer. The first metal layer and the second metal layer are disposed on opposite sides of the die, respectively. The electrical connection component is disposed in the encapsulation layer. The first metal layer is electrically connected with the second metal layer through the electrical connection component. The electrical connection component includes a non-metal core and a metal film located on a surface of the non-metal core.

Abstract: The present disclosure relates to a solid state micro device structure that has a microdevice formed on a substrate, with p and n doped layers, active layers between at least the two doped layers, pads coupled to each doped layer, and wherein the n-doped layer is modulated to have a lower conductivity towards an edge of the device. The invention further involves, dielectric layer, conductive layer, passivation layer and MIS structure.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a contact structure. The substrate includes a shallow trench isolation (STI) structure and active structures separated by the STI structure. The contact structure includes a first contact structure and a second contact structure that are laminated, where the first contact structure covers a part of a top surface and a part of a side wall of the active structure.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nanostructure (e.g., nanosheet, nanowire, or the like) GAA devices. A vertically stacked nanostructure GAA device may be formed with a topmost channel region that is thinner than a bottommost channel region. Furthermore, the topmost channel region of the GAA device may be formed with lightly doped drain regions with a highest concentration and/or a greater degree of lateral diffusion of implanted dopants as compared to the bottommost channel region.

Abstract: A fin field-effect transistor device with hybrid conduction mechanism, including a fin field-effect transistor, a second source region, and a second drain region; the fin field-effect transistor includes a substrate, a fin channel region, a first source region, and a first drain region; the height of the second source region is not lower than the height of the substrate between the first source region and the first drain region; the first source region the first drain region and the second drain region are doped with first ions; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, the second source region is doped with second ions. This scheme can realize hybrid conduction of fin channel diffusion drift current and bottom channel band-to-band tunneling current, thus obtaining better ultra-steep switching characteristics.

Abstract: A memory structure includes a plurality of memory cells arranged in an array. Each of the memory cells includes a memory region, a word line portion disposed on a first surface of the memory region, a first conductive block disposed on a second surface of the memory region opposite to the first surface, a second conductive block disposed on the second surface of the memory region, and a third conductive block disposed on the second surface of the memory region such that the third conductive block is disposed between and separated from the first conductive block and the second conductive block.

Abstract: An integrated circuit device includes a substrate and a memory device. The memory device is over the substrate. The memory device includes a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode. The dielectric layer is over the bottom electrode. The antiferroelectric layer is over the dielectric layer. The top electrode is over the antiferroelectric layer.

Abstract: A non-volatile memory device includes: an insulation layer; a Schottky diode, which is formed on the insulation layer; a writing wire which is conductive and is electrically connected to a first end of the Schottky diode; a memory unit on the Schottky diode, the memory unit being electrically connected to a second end of the Schottky diode; and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the Schottky diode to write the data into the memory unit.