Patents Examined by David Vu
  • Patent number: 11031243
    Abstract: A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 8, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey C. Gardner, Sergei V. Gronin, Raymond L. Kallaher
  • Patent number: 11031471
    Abstract: A semiconductor device is provided, including: a first conductivity-type drift region formed in the semiconductor substrate; a second conductivity-type base region formed between the upper surface of the semiconductor substrate and the drift region; a first conductivity-type accumulation region formed between the drift region and the base region and having a higher doping concentration than the drift region; and a dummy trench portion formed to penetrate the base region from the upper surface of the semiconductor substrate, wherein at least one of the accumulation region and the dummy trench portion has a suppressing structure that suppresses formation of a second conductivity-type inversion layer in a first conductivity-type region adjacent to the dummy trench portion.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 8, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 11031458
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chih-Fan Huang, Chih-Yang Pai, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11031412
    Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Chi Wu, Yu-Wen Tseng
  • Patent number: 11024564
    Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tianyi Luo, Jonathan Almeria Noquil, Osvaldo Jorge Lopez
  • Patent number: 11024591
    Abstract: A wireless communication module with improved performance and a mobile object that is equipped with the wireless communication module with the improved performance are provided. The mobile object is equipped with a wireless communication module. The wireless communication module includes a substrate, a first element, and a second element. The substrate includes ground layers. The first element is arranged on the substrate and amplifies an input RF signal. The second element is arranged on the substrate and different from the first element. Each of the ground layers has a groove formed between the first element and the second element.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 1, 2021
    Assignee: KYOCERA CORPORATION
    Inventor: Takumi Ogata
  • Patent number: 11018301
    Abstract: A method for the contacting of electrodes with conductor tracks by means of a conductive paste and/or adhesive-coated conductive fiber composites is provided. Furthermore, an electronic component whose electrodes are connected by means of a conductive paste and/or adhesive-coated conductive fiber composites is provided.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: May 25, 2021
    Assignee: INURU GMBH
    Inventors: Patrick Barkowski, Marcin Ratajczak
  • Patent number: 11018143
    Abstract: An antifuse One-Time-Programmable memory cell includes a substrate, and a hybrid select transistor and a hybrid antifuse capacitor formed on the substrate. The hybrid select transistor includes a first gate dielectric layer formed on the substrate, wherein the first gate dielectric layer is thinner than 40 nm, a first high-voltage junction formed in the substrate, and a low-voltage junction formed in the substrate. The hybrid antifuse capacitor includes a second gate dielectric layer, wherein the second gate dielectric layer is thinner than 40 nm, which enables a low-voltage antifuse capacitor device, a second gate formed on the gate dielectric layer, a second high-voltage junction formed in the substrate, and a third high-voltage junction formed in the substrate.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 25, 2021
    Assignee: Zhuhai Chuangfeixin Technology Co., Ltd.
    Inventors: Li Li, Zhigang Wang
  • Patent number: 11018061
    Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
  • Patent number: 11011415
    Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
  • Patent number: 11011418
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 18, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
  • Patent number: 11011467
    Abstract: A method includes depositing an etch stop layer over a non-insulator structure and a dielectric layer over the etch stop layer; etching the dielectric layer to form a first hole in the dielectric layer; deepening the first hole into the etch stop layer such that the non-insulator structure is exposed at a bottom of the deepened hole; after the non-insulator structure is exposed, performing a cleaning operation to remove etch byproducts from the deepened first hole, wherein the cleaning operation results in lateral recesses laterally extending from a bottom portion of the deepened first hole into the etch stop layer; depositing a first diffusion barrier layer into the deepened first hole until the lateral recesses are overfilled; depositing a second diffusion barrier layer over the first diffusion barrier layer; and depositing one or more conductive layers over the second diffusion barrier layer.
    Type: Grant
    Filed: August 8, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 11011730
    Abstract: Provided is a display device including: a structure including a display area and a peripheral area surrounding the display area; and an inorganic encapsulation thin film disposed on the display and peripheral areas. The peripheral area includes at least one inorganic surface portion having a closed shape continuously.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 18, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Myoung-Seo Park
  • Patent number: 11011535
    Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
  • Patent number: 11011713
    Abstract: The present disclosure provides a display module and an electronic apparatus. The display module includes: a flexible substrate having: a first surface configured to form a displaying structure, and a second surface opposite to the first surface; and a protective part located on the second surface and having a supporting portion. The flexible substrate includes: a substrate body having a first subsurface which is a portion of the second surface corresponding to the substrate body; and a bent portion located at at least one side of the substrate body, bent towards the first subsurface of the substrate body, and having a second subsurface which is a portion of the second surface corresponding to the bent portion. The second subsurface is supported by the supporting portion such that a radius of curvature of the bent portion : is not less than a minimal radius of curvature which the flexible substrate is capable of withstanding.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 18, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Shangchieh Chu
  • Patent number: 11005033
    Abstract: A component semiconductor structure having a semiconductor layer, which has a front side and a back side, at least one integrated circuit being formed on the front side and a first oxide layer being formed on the back side, a monolithically formed semiconductor body having a top surface and a back surface being provided, and a second oxide layer being formed on the back surface, and the two oxide layers being integrally connected to each other, and a sensor region formed between the top surface and the back surface and having a three-dimensional isotropic Hall sensor structure being disposed in the semiconductor body, the Hall sensor structure extending from a buried lower surface up to the top surface, and at least three first highly doped semiconductor contact regions being formed on the top surface and at least three second highly doped semiconductor contact regions being formed on the lower surface.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 11, 2021
    Assignee: TDK-Micronas GmbH
    Inventors: Martin Cornils, Maria-Cristina Vecchi
  • Patent number: 11004813
    Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 11, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Patent number: 10998350
    Abstract: Provided is a display device including a display panel including a pixel including a first sub-pixel and a second sub-pixel, and a capping layer. The first sub-pixel includes a first pixel transistor disposed on a first pixel circuit area, a first pixel electrode disposed on a first pixel electrode area, a first color filter disposed on the first pixel circuit area while covering the first pixel transistor, and a second color filter disposed on the first pixel electrode area and the first pixel circuit area. The capping layer covers the first color filter and the second color filter, and a first opening is defined in one area of the capping layer, which overlaps the second color filter on a plane.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 4, 2021
    Inventors: Jinjoo Ha, Basrur Veidhes, Yangho Bae, Changil Tae
  • Patent number: 10998322
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 4, 2021
    Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Taejin Park, Yoosang Hwang
  • Patent number: 10998514
    Abstract: A photoelectric device includes a first photoelectric conversion layer including a heterojunction that includes a first p-type semiconductor and a first n-type semiconductor, a second photoelectric conversion layer on the first photoelectric conversion layer and including a heterojunction that includes a second p-type semiconductor and a second n-type semiconductor. A peak absorption wavelength (?max1) of the first photoelectric conversion layer and a peak absorption wavelength (?max2) of the second photoelectric conversion layer are included in a common wavelength spectrum of light that is one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, a blue wavelength spectrum of light, a near infrared wavelength spectrum of light, or an ultraviolet wavelength spectrum of light, and a light-absorption full width at half maximum (FWHM) of the second photoelectric conversion layer is narrower than an FWHM of the first photoelectric conversion layer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Bae Park, Takkyun Ro, Kiyohiko Tsutsumi, Chul Joon Heo, Yong Wan Jin