Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having a first horizontally extending surface and a second horizontally extending surface above the first horizontally extending surface as viewed in a cross-sectional view. The first horizontally extending surface continuously wraps around an outermost perimeter of the second horizontally extending surface in a closed loop as viewed in a plan-view. A second substrate is disposed over the first substrate and includes a third horizontally extending surface above the second horizontally extending surface as viewed in the cross-sectional view. The second horizontally extending surface continuously wraps around an outermost perimeter of the third horizontally extending surface in a closed loop as viewed in the plan-view.

Abstract: A two-terminal memory device includes: a substrate; an extended drain extending from a drain and a lower surface of the drain and laminated on the substrate; a ferroelectric layer connected to the drain and covering the extended drain and the substrate; and a source laminated on the ferroelectric layer to face the drain.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a protruding structure over a substrate. The protruding structure has multiple sacrificial layers and multiple semiconductor layers, and the sacrificial layers and the semiconductor layers have an alternating configuration. The method also includes forming a gate stack to wrap a portion of the protruding structure. The method further includes forming an epitaxial structure abutting edges of the semiconductor layers. The formation of the epitaxial structure includes forming a lower semiconductor portion on a bottom of the recess and forming an upper semiconductor portion over the lower semiconductor portion. The upper semiconductor portion and the lower semiconductor portion are oppositely doped.

Abstract: A foldable display, includes a display layer with flexibility including a first display region, a second display region, and a third display region located between the first display region and the second display region; a cover with flexibility configured to cover the display layer; a first support substrate with inflexibility configured to support the first display region; a second support substrate with inflexibility configured to support the second display region; a bending part capable of bending including the third display region; and a shock absorbing layer provided between the display layer and the first support substrate and between the display layer and the second support substrate.

Abstract: A display panel includes at least one pixel unit. The pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel. The first, second, third and fourth sub-pixels include a first color filter portion, second color filter portion, a third color filter portion and a fourth color filter portion, respectively. The first, second and third color filter portions are configured to emit light of three primary colors. A material of the fourth color filter portion includes at least one light conversion material configured to convert a portion of light directed to the fourth color filter portion into light of at least one primary color. The light of at least one primary color is capable of being mixed with another portion of the light directed to the fourth color filter portion to generate white light.

Abstract: A display device includes a data line transmitting a data voltage to each pixel, a power line supplying current to each pixel, wherein the data line and the power line are disposed on a substrate and extended along a first direction, a light shielding layer shielding a light emitting diode from light coming from outside, a gate line transmitting a gate voltage to each pixel and extended along a second direction intersecting the first direction, a gate insulating layer and a buffer layer disposed between the data line and the gate line, wherein the data line and the power line are disposed on a same layer as the light shielding layer.

Abstract: An image sensor includes a substrate including a first region and a second region surrounding the first region, a light sensing element in the substrate, a planarization layer on the light sensing element, a color filter array layer including color filters on the planarization layer on the first region of the substrate, a light blocking metal pattern on the planarization layer on the second region of the substrate, a dummy color filter layer on the light blocking metal pattern on a portion of the second region adjacent to the first region of the substrate, and microlens on the color filter array layer. Active pixels are in the first region, and optical black (OB) pixels are in the second region.

Abstract: A display panel includes: a substrate; a transistor on the substrate; a planarization layer on the transistor, and defining at least one recess; a first pixel electrode and a second pixel electrode on the planarization layer, with the recess therebetween in a plan view; a metal pattern on the planarization layer, and adjacent to the first pixel electrode or the second pixel electrode; a pixel defining layer on the metal pattern and filling the recess; and a spacer on the pixel defining layer and overlapping with the metal pattern.

Abstract: FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.

Abstract: A magnetoresistive element that has a magnetic material made of an alloy having a stable bcc structure containing Co as a main component, has an excellent tunnel magnetoresistive ratio, and can be put into practical use by mass production, and a magnetic storage device using the magnetoresistive element are provided. The magnetoresistive element includes a first magnetic layer whose magnetization direction is substantially fixed, a second magnetic layer whose magnetization direction is changeable, and a non-magnetic layer arranged between the first magnetic layer and the second magnetic layer. The first magnetic layer and/or the second magnetic layer has an alloy having a bcc structure containing Co as a main component and Co and Mn.

Abstract: A nonvolatile memory device with improved reliability is provided. The nonvolatile memory device comprises a substrate, a mold structure including a plurality of word lines stacked on the substrate, a first word line cut region configured to cut the mold structure, a first channel structure spaced apart from the first word line cut region by a first distance, and disposed in the mold structure and the substrate, and a second channel structure spaced apart from the first word line cut region by a second distance, and disposed in the mold structure and the substrate, wherein the second distance is greater than the first distance, a first width of the first channel structure is different from a second width of the second channel structure, and a first length of the first channel structure is different from a second length of the second channel structure.

Abstract: A method for manufacturing a semiconductor device includes: irradiating, with laser light, a semiconductor substrate having a p-type first semiconductor layer and an n-type second semiconductor layer so that the laser light converges on an interface between the first semiconductor layer and the second semiconductor layer, wherein each of the p-type first semiconductor layer and the n-type second semiconductor layer placed on the first semiconductor layer is formed of a compound semiconductor; and separating the semiconductor substrate into the first semiconductor layer and the second semiconductor layer along the interface.

Abstract: An electronic device is provided. The electronic device has a first portion and a second portion adjacent to the first portion. The electronic device includes a sensing element and a plurality of first patterns and a plurality of second patterns. The sensing element is configured to receive a light corresponding to the first portion. The plurality of first patterns and the plurality of second patterns are corresponding to the second portion and configured to absorb different colors of lights. Moreover, an area of one of the plurality of first patterns is different from an area of one of the plurality of second patterns.

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. In the semiconductor device, a supporting pattern may be used to fix upper portions of active patterns, when a gap-filling process is performed to fill a region between active patterns, and thus, it may be possible to prevent or reduce the likelihood of the active patterns from being bent or fallen. Thus, it may be possible to reduce failure of the semiconductor device and/or to improve reliability of the semiconductor device.

Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.

Abstract: As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located over the alternating stack, a dielectric spacer layer located over the semiconductor material layer, a memory opening vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, a memory opening fill structure located in the memory opening and including a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film, and a source layer located over the dielectric spacer layer and contacting the pillar portion. In one embodiment, a tubular spacer laterally surrounds the pillar portion, is laterally spaced from the pillar portion by a cylindrical portion of the memory film, and contacts a cylindrical sidewall of the semiconductor material layer.

Abstract: The present invention relates to a method for manufacturing a solar cell, comprising: a seating process of seating, in a processing space for manufacturing a solar cell, a cell in which a plurality of thin film layers are formed; a coating process of spraying a conductive material onto the cell; and a scribing process of irradiating a laser toward the cell to form a cell separation unit for separating the cell into a plurality of unit cells.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.