Patents Examined by David Vu
  • Patent number: 10707390
    Abstract: An area light source display module is provided. The area light source display module includes a substrate and a light emitting diode (LED) array disposed on the substrate. A plurality of LED particles disposed on the LED array emit wide-angle light. Each of the LED particles has a lower light intensity distribution at a center of 0° and a higher light intensity distribution at an off-center polar angle ?. ? ranges between 30 degrees and 80 degrees. The LED array includes LED particles emitting the wide-angle light. Therefore, the area light source module can adopt fewer LEDs at a same thickness of the light source display module with an LED having a common light shape, or the area light source module can have a smaller light mixing distance with the same number of LEDs.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 7, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Guowei Zha
  • Patent number: 10707374
    Abstract: A method of forming a light emitting device includes forming a growth mask layer including openings on a doped compound semiconductor layer, forming first light emitting diode (LED) subpixels by forming a plurality of active regions and second conductivity type semiconductor material layers employing selective epitaxy processes, and transferring each first LED subpixel to a backplane. An anode contact electrode may be formed on the second conductivity type semiconductor material layers for redundancy. The doped compound semiconductor layer may be patterned with tapered sidewalls to enhance etendue. An optically clear encapsulation matrix may be formed on the doped compound semiconductor material layer to enhance etendue. Lift-off processes may be employed for the active regions. Cracking of the LEDs may be suppressed employing a thick reflector layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 7, 2020
    Assignee: GLO AB
    Inventors: Fariba Danesh, Benjamin Leung, Tsun Lau, Zulal Tezcan, Miao-Chan Tsai, Max Batres, Michael Joseph Cich
  • Patent number: 10707134
    Abstract: FinFET structures and fabrication methods thereof are provided. An exemplary fabrication method includes forming a semiconductor substrate and a plurality of fins. First trenches and second trenches are formed between adjacent fins, and a width of the first trench is greater than a width of the second trench. The method also includes forming a first isolation layer on the semiconductor substrate exposed by the fins and on side surfaces of the fins. The first isolation layer containing an opening at the first trench. Further, the method also includes performing a first thermal annealing; forming a second isolation layer to fill the opening; removing a partial thickness of the first isolation layer and a partial thickness of the second layer to form an isolation structure; forming a gate structure across the plurality of fins; and forming doped source/drain regions in the fins at two sides of the gate structure.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 7, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Ji Quan Liu
  • Patent number: 10707269
    Abstract: According to one embodiment, a semiconductor storage device includes: a first memory cell and a second memory cell, each including a switching element and a resistance change element coupled to the switching element, and the first memory cell and the second memory cell being adjacent to each other; a non-active member having a switching function between the switching element of the first memory cell and the switching element of the second memory cell; and an insulator which covers at least one of an upper surface or a lower surface of the non-active member, a side surface of the non-active member, a side surface of the switching element of the first memory cell, and a side surface of the switching element of the second memory cell.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toshihiko Nagase, Daisuke Watanabe, Koji Ueda, Tadashi Kai, Kazumasa Sunouchi
  • Patent number: 10707143
    Abstract: A plug-in type power module includes a power unit and a heat-transfer unit vertically disposed on the power unit and extending outwardly away from two sides of the power unit. A first ceramic layer is disposed between the power unit and the heat-transfer unit. Therefore, heat generated by the power unit can be transferred from the first ceramic layer to the heat-transfer unit to increase the speed of heat dissipation. A subsystem having the plug-in type power module is also provided.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 7, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Jung Yang, Yu-Lin Chao, Chun-Kai Liu, Ming Kaan Liang, Jiin Shing Perng
  • Patent number: 10704744
    Abstract: A light source unit is disclosed in an embodiment. The disclosed light source unit comprises: a fixing plate having an opening portion; a light emitting device disposed in an opening portion of the fixing plate; and an optical lens disposed on the fixing plate, wherein the fixing plate has a plurality of fixing portions, the optical lens includes: a bottom surface on the fixing plate; a concave recess on the opening portion of the fixing plate; a light incident surface around the recess; and a light exit surface for emitting the light incident to the light incident surface, the fixing plate and the bottom surface of the optical lens are coupled to each other, and the fixing plate is spaced from the light emitting device.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: July 7, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Sung Joo Oh
  • Patent number: 10700243
    Abstract: A light emitting device includes a light emitting element having an emission peak wavelength in a range of 380 nm or more and 490 nm or less, and a red fluorescent material which is excited by the light from the light emitting element to emit light having at least one light emission peak wavelength in a range of 580 nm or more and 680 nm or less, wherein a ratio of the photon flux R of red light in a range of 620 nm or more and 700 nm or less to the photon flux B of blue light in a range of 400 nm or more and 490 nm or less, R/B, is in a range of more than 20 and 200 or less.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 30, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Mika Amiya, Kazushige Fujio, Sadakazu Wakui
  • Patent number: 10699962
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: June 30, 2020
    Assignee: Tessera, Inc.
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10700105
    Abstract: An array substrate, a method for manufacturing an array substrate, a display panel and a display device are provided. The array substrate includes: a base substrate including a display area and a non-display area; a dummy data line in the non-display area of the base substrate; and an effective data line in the non-display area of the base substrate. The dummy data line is closer to an edge of the base substrate than the effective data line, and a width of the dummy data line is greater than a width of the effective data line.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 30, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yanfeng Li, Yanan Yu, Jingyi Xu, Xin Zhao, Xiaokang Wang, Yanwei Ren, Wei Li
  • Patent number: 10700198
    Abstract: A semiconductor device includes a substrate, a first P-type well region and a second P-type well region disposed in the substrate, wherein the first P-type well region and the second P-type well region are spaced apart from each other, an N-type source region disposed in the substrate, wherein the N-type source region is disposed spaced apart from the second P-type well region, an N-type drain region disposed in the second P-type well region, an N-type LDD region disposed near the N-type drain region, and a gate insulating layer and a gate electrode on the substrate, wherein the gate electrode partially overlaps the second P-type well region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 30, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Jin Yeong Son, Hee Hwan Ji
  • Patent number: 10692987
    Abstract: The disclosure provides an integrated circuit (IC) structure including a first spacer on a semiconductor fin adjacent a first portion of the gate structure, and having a first height above the semiconductor fin; a second spacer on the semiconductor fin adjacent the first spacer, such that the first spacer is horizontally between the first portion of the gate structure and a lower portion of the outer; and a gate cap positioned over the first portion of the gate structure and on the second spacer above the semiconductor fin. The gate cap defines an air gap horizontally between the first portion of the gate structure and an upper portion of the second spacer, and vertically between an upper surface of the first spacer and a lower surface of the gate cap.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Guowei Xu, Hui Zang
  • Patent number: 10693098
    Abstract: Light-emitting devices having an emitting layer containing a light-emitting organic or organometallic material and a nanostructure, the nanostructure having strong local electric fields at visible electromagnetic wavelengths that spectrally and spatially overlap with the light-emitting material. The spectral and spatial overlap of the electric fields of the nanostructure with the light emitting material uses high LDOS provided by the nanostructures to enable excited triplet electronic states in the material to emit light faster than without the nanostructure. This faster light emission from triplet-excited states leads to more stable emission from the light emitting material because it prevents buildup of triplet-excited states, which ordinarily can lead to quenching of light emission from the light emitting material. Among the many different possibilities contemplated, the nanostructure may advantageously be made of a dielectric material or a plasmonic metal material, such as SiO2, TiO2, ZnO, Al or Ag.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: June 23, 2020
    Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY
    Inventor: Deirdre O'Carroll
  • Patent number: 10683204
    Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chung-Yen Chou, Lee-Chuan Tseng, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10686071
    Abstract: A semiconductor device including a first P-type well region and an asymmetric second P-type well region each formed in a semiconductor substrate; a gate insulating layer and a gate electrode formed on the substrate; a first N-type source/drain region and a second N-type source/drain region that are formed on respective sides of the gate electrode; and an asymmetric LDD region of N-type formed to extend from the second source/drain region, wherein the asymmetric second P-type well region encompasses the second N-type source/drain region and the asymmetric LDD region, and the first N-type source/drain region both the asymmetric second P-type well region and the substrate, and the asymmetric second P-type well region is formed encompassing the second N-type source/drain region and in contact with the first N-type source/drain region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 16, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Hyung Jang, Hee Hwan Ji, Jin Yeong Son
  • Patent number: 10685925
    Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 16, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Patent number: 10685923
    Abstract: An electronic chip including a plurality of buried doped bars and a circuit for detecting an anomaly of an electric characteristic of the bars.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 16, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Jimmy Fort, Thierry Soude
  • Patent number: 10686129
    Abstract: A memory cell includes: a first electrode contact formed as a cylinder shape that extends along a first direction; a resistive material layer comprising a first portion that extends along the first direction and surrounds the first electrode contact; and a second electrode contact coupled to the resistive material layer, wherein the second electrode contact surrounds the first electrode contact and the first portion of the resistive material layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Mo, Shih-Chi Kuo
  • Patent number: 10686017
    Abstract: A display device may include a display panel including a substrate that includes a display area and a pad area adjacent to the display area, and a first pad and a second pad on the pad area of the substrate, and a chip-on-film package over the pad area of the substrate with the first pad and the second pad in between, the chip-on-film package including an insulation layer, a first wiring on an upper surface of the insulation layer and electrically connected to the first pad, and a second wiring on a lower surface of the insulation layer and electrically connected to the second pad. A first signal having alternating voltage levels may be applied to the first wiring, and a second signal having a constant voltage level may be applied to the second wiring.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Cheolhwan Eom, Kwang-Min Kim, Hyeaweon Shin, Sang Joon Ryu, Hyungjun An, Minji Lee, Yul Kyu Lee, Jeahyun Lee
  • Patent number: 10680080
    Abstract: A method for manufacturing a semiconductor device includes forming a gate insulation film and a polysilicon layer on a substrate, forming a polysilicon pattern by etching the polysilicon layer, forming an opening in the polysilicon pattern that exposes a part of the polysilicon pattern by forming a mask pattern on the polysilicon pattern, forming a gate electrode by etching the part of the polysilicon pattern exposed through the opening, forming a P-type body region by ion implanting a P-type dopant onto the substrate using the gate electrode as a mask, forming an N-type LDD region on the P-type body region by ion implanting an N-type dopant onto the substrate using the gate electrode as a mask, forming a spacer on a side surface of the gate electrode, and forming an N-type source region on a side surface of the spacer.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: June 9, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Tae Hoon Lee, Jun Hee Cho, Jin Seong Chung
  • Patent number: 10679934
    Abstract: A semiconductor interconnect structure and a method of fabricating the same are provided. The semiconductor interconnect structure includes a sea of interconnect lines including metal lines and neighboring dummy lines. The semiconductor interconnect structure further includes a dielectric layer arranged between the sea of lines.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Huai Huang, Christopher J. Penny, Michael Rizzolo, Hosadurga Shobha