Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.

Abstract: A three-dimensional semiconductor memory device includes: a peripheral circuit structure; and a cell array structure on the peripheral circuit structure. The peripheral circuit structure includes a lower wiring on a substrate, a stopping insulating layer on the lower wiring, a contact via on the lower wiring, a floating via on the stopping insulating layer, and an upper wiring on the contact via. The floating via does not contact the lower wiring. The contact via contacts the lower wiring through a via hole in the stopping insulating layer. The upper wiring contacts the contact via.

Abstract: Provided is a stable CdZnTe monocrystalline substrate having a small leakage current even when a high voltage is applied and having a lower variation in resistivity with respect to variations in applied voltage values. A semiconductor wafer comprising a cadmium zinc telluride monocrystal having a zinc concentration of 4.0 at % or more and 6.5 at % or less and a chlorine concentration of 0.1 ppm by mass or more and 5.0 ppm by mass or less, wherein the semiconductor wafer has a resistivity of 1.0×107 ?cm or more and 1.0×108 ?cm or less when a voltage of 900 V is applied, and wherein a ratio (variation ratio) of the resistivity at application of 0 V to the resistivity at application of a voltage of 900 V is 20% or less.

Abstract: A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

Abstract: A semiconductor memory device and a method for fabricating the same are provided. The semiconductor memory device includes a plurality of gate stacks separated by a plurality of slit structures, and each of the gate stacks includes: a first stack including three or more first conductive patterns spaced apart from one another at substantially a same level; a second stack formed on the first stack and including second conductive patterns and interlayer dielectric layers alternately stacked; and a plurality of channel structures penetrating the second stack and the first stack.

Abstract: According to one embodiment, a semiconductor storage device is provided which includes a stacked body, a first pillar portion, a first separating portion, and a first supporting post. In the stacked body, a plurality of insulating layers and a plurality of electrically conductive layers are stacked alternately one on another. The stacked body is provided on a predetermined electrically conductive film. The first pillar portion includes a plurality of memory cells, and penetrates through the stacked body in a stacking direction of the stacked body. The first separating portion separates the stacked body into a plurality of blocks. The first supporting post extends locally within the stacked body from an upper surface of the predetermined electrically conductive film in the stacking direction.

Abstract: An integrated circuit device includes a peripheral circuit structure arranged on a substrate, a gate stack arranged on the peripheral circuit structure and including a plurality of gate electrodes, and a dam structure formed in a dam opening portion that passes through the gate stack. The dam structure includes an insulation spacer on an inner wall of the dam opening portion and a pair of sloped sidewalls at an upper side of the dam opening portion, and a buried layer filling an inside of the dam opening portion and including an air space. The integrated circuit device further includes a mold gate stack surrounded by the dam structure and including a plurality of mold layers, a plurality of conductive lines arranged on the gate stack, and a plurality of through electrodes connected to the plurality of conductive lines, passing through the mold gate stack, and surrounded by the dam structure.

Abstract: A transistor substrate may include a substrate including a first region and a second region, a first buffer layer disposed in the first region on the substrate and including silicon nitride, a second buffer layer disposed in the first region and the second region on the first buffer layer and including silicon oxide, a first transistor disposed in the first region on the second buffer layer and including a first oxide semiconductor layer and a first gate electrode overlapping the first oxide semiconductor layer, and a second transistor disposed in the second region on the second buffer layer and including a second oxide semiconductor layer and a second gate electrode overlapping the second oxide semiconductor layer.

Abstract: A deposition mask for manufacturing a display panel includes a metallic base having a thickness of about 50 micrometers to about 200 micrometers and a plurality of openings defined therein, wherein at least some of the openings include a first opening having a first width and a second opening having a second width smaller than the first width respectively defined along a thickness direction of the metallic base, and wherein the metallic base includes a first part in which the first opening is defined, and a second part in which the second opening is defined, the second part having a width that increases in a direction downward from a top surface of the metallic base along the thickness direction of the metallic base.

Abstract: An apparatus for growing semiconductor wafers, in particular of silicon carbide, wherein a chamber houses a collection container and a support or susceptor arranged over the container. The support is formed by a frame surrounding an opening accommodating a plurality of arms and a seat. The frame has a first a second surface, opposite to each other, with the first surface of the frame facing the support. The arms are formed by cantilever bars extending from the frame into the opening, having a maximum height smaller than the frame, and having at the top a resting edge. The resting edges of the arms define a resting surface that is at a lower level than the second surface of the frame. The seat has a bottom formed by the resting surface.

Abstract: A transparent multi-layer assembly includes a transparent carrier structure comprising a polymer material and an electrically conductive transparent layer comprising an electrically conductive oxide. A silicon carbide layer is arranged as an adhesion promoter between the transparent carrier structure and the electrically conductive transparent layer.

Abstract: A semiconductor memory device includes a tunnel insulating layer, a data storage layer, and a blocking insulating layer that are sequentially disposed. The tunnel insulating layer includes Metal Organic Frameworks (MOF) having a lower dielectric constant than a dielectric constant of the blocking insulating layer.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: A display device includes a pixel in a display area. The pixel includes a first electrode and a second electrode that are spaced apart from each other, a first insulating layer disposed on the first and second electrodes and including a trench corresponding to a region between the first and second electrodes, light emitting elements disposed in the trench, each of the light emitting elements including a first end portion and a second end portion, a first contact electrode disposed on the first end portion of each of the light emitting elements and the first electrode, and a second contact electrode disposed on the second end portion of each of the light emitting elements and the second electrode. The trench includes a first trench accommodating the light emitting elements, and second trenches disposed in the first trench.

Abstract: In some implementations, one or more semiconductor processing tools may form a via for a semiconductor device. The one or more semiconductor processing tools may deposit a metal plug within the via. The one or more semiconductor processing tools may deposit an oxide-based layer on the metal plug within the via. The one or more semiconductor processing tools may deposit a resistor on the oxide-based layer within the via. The one or more semiconductor processing tools may deposit a first landing pad and a second landing pad on the resistor within the via. The one or more semiconductor processing tools may deposit a first metal plug on the first landing pad and a second metal plug on the second landing pad.

Abstract: A display device includes pixel circuits disposed on a substrate, each of the pixel circuits comprising a transistor and a storage capacitor, display elements electrically connected to the pixel circuits, and a metal layer disposed between the substrate and the pixel circuits, the metal layer comprising through-holes, wherein the through-holes of the metal layer include a first through-hole, and a second through-hole disposed adjacent to the first through-hole.

Abstract: Aspects of the subject disclosure include a pressure-sensing device consisting of a housing including a membrane and one or more piezoresistive elements disposed on the membrane to sense a displacement due to a deflection of the membrane. A first set of electrodes is disposed over the membrane, and a second set of electrodes is disposed on a permeable port of the device at a distance from the membrane. The first and second sets of electrodes form an electrostatic actuator to exert a repulsive force onto the membrane to reduce the deflection of the membrane.

Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

Abstract: An optical semiconductor device includes an optical semiconductor chip in which at least one optical element is formed in a semiconductor substrate, and an extended wire pattern that is connected to a first electrode and a second electrode of the optical element and that extends outside the optical semiconductor chip. The first electrode and the second electrode of the optical semiconductor device are formed on the front surface side of the optical semiconductor chip, and the extended wire pattern is disposed on the front surface of the optical semiconductor chip or disposed at a position apart from the front surface.

Abstract: Provided is a display substrate, including: a silicon-based substrate having a display area, a binding area located on one side of the display area, and a trace area located between the display area and the binding area; a trace protection structure is arranged on the silicon-based substrate in the trace area, and a pad assembly is integrated in the silicon-based substrate in the binding area; and a minimum distance between an edge of an orthographic projection of the trace protection structure on the silicon-based substrate and an edge of an orthographic projection of an opening of the pad assembly on the silicon-based substrate is smaller than a maximum size of one subpixel.