Patents Examined by David Vu
  • Patent number: 11011418
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 18, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
  • Patent number: 11011730
    Abstract: Provided is a display device including: a structure including a display area and a peripheral area surrounding the display area; and an inorganic encapsulation thin film disposed on the display and peripheral areas. The peripheral area includes at least one inorganic surface portion having a closed shape continuously.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 18, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Myoung-Seo Park
  • Patent number: 11011415
    Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Rasit O. Topaloglu, Naftali Lustig, Matthew Angyal
  • Patent number: 11011535
    Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wang Xiang, Chia-Ching Hsu, Shen-De Wang, Weichang Liu
  • Patent number: 11011713
    Abstract: The present disclosure provides a display module and an electronic apparatus. The display module includes: a flexible substrate having: a first surface configured to form a displaying structure, and a second surface opposite to the first surface; and a protective part located on the second surface and having a supporting portion. The flexible substrate includes: a substrate body having a first subsurface which is a portion of the second surface corresponding to the substrate body; and a bent portion located at at least one side of the substrate body, bent towards the first subsurface of the substrate body, and having a second subsurface which is a portion of the second surface corresponding to the bent portion. The second subsurface is supported by the supporting portion such that a radius of curvature of the bent portion : is not less than a minimal radius of curvature which the flexible substrate is capable of withstanding.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 18, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Shangchieh Chu
  • Patent number: 11011467
    Abstract: A method includes depositing an etch stop layer over a non-insulator structure and a dielectric layer over the etch stop layer; etching the dielectric layer to form a first hole in the dielectric layer; deepening the first hole into the etch stop layer such that the non-insulator structure is exposed at a bottom of the deepened hole; after the non-insulator structure is exposed, performing a cleaning operation to remove etch byproducts from the deepened first hole, wherein the cleaning operation results in lateral recesses laterally extending from a bottom portion of the deepened first hole into the etch stop layer; depositing a first diffusion barrier layer into the deepened first hole until the lateral recesses are overfilled; depositing a second diffusion barrier layer over the first diffusion barrier layer; and depositing one or more conductive layers over the second diffusion barrier layer.
    Type: Grant
    Filed: August 8, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 11005033
    Abstract: A component semiconductor structure having a semiconductor layer, which has a front side and a back side, at least one integrated circuit being formed on the front side and a first oxide layer being formed on the back side, a monolithically formed semiconductor body having a top surface and a back surface being provided, and a second oxide layer being formed on the back surface, and the two oxide layers being integrally connected to each other, and a sensor region formed between the top surface and the back surface and having a three-dimensional isotropic Hall sensor structure being disposed in the semiconductor body, the Hall sensor structure extending from a buried lower surface up to the top surface, and at least three first highly doped semiconductor contact regions being formed on the top surface and at least three second highly doped semiconductor contact regions being formed on the lower surface.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 11, 2021
    Assignee: TDK-Micronas GmbH
    Inventors: Martin Cornils, Maria-Cristina Vecchi
  • Patent number: 11004813
    Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 11, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Masanori Shindo
  • Patent number: 10998322
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 4, 2021
    Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Taejin Park, Yoosang Hwang
  • Patent number: 10995928
    Abstract: The base member (300) has a light transmitting property. The light emitting element (20) is on the inner surface (302) of the base member (300). The light emitting element (20) includes a light emitting portion (142) and a light transmitting portion (144). A plurality of wirings (222) of the first sheet 202 and a plurality of wirings (222) of the second sheet (204) are on the surface of the base member (300). The plurality of wirings (222) of the first sheet (202) is electrically connected to an anode (first terminal (112)) of the light emitting element (20). The plurality of wirings (222) of the second sheet (204) is electrically connected to a cathode (second terminal (132)) of the light emitting element (20).
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: May 4, 2021
    Assignee: PIONEER CORPORATION
    Inventor: Takeshi Nakamura
  • Patent number: 10998375
    Abstract: Disclosed are light emitting modules and automobile illumination devices including the same. The light emitting module comprises a module substrate, a light emitting device on the module substrate, and a light guide structure apart from the module substrate and in plan view surrounding the light emitting device. The light emitting device comprises a first pixel and a second pixel each including a light emitting diode (LED) chip that emits light whose wavelength falls within a range of blue color or ultraviolet ray, and a wavelength conversion material on a top surface of at least one of the first and second pixels.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Lee, Namhyeok Kwak, Gunduk Kim, Seungwoo Lee, Do-Hun Kim, Heedong Kim
  • Patent number: 10998513
    Abstract: A display device is disclosed. In one aspect, the display device includes a flexible substrate capable of being bent in a first direction and an insulating layer including a first opening pattern positioned on the flexible substrate and extending in a second direction crossing the first direction.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 4, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae Woong Kim, Hyun Woo Koo, Young Gug Seol
  • Patent number: 10998350
    Abstract: Provided is a display device including a display panel including a pixel including a first sub-pixel and a second sub-pixel, and a capping layer. The first sub-pixel includes a first pixel transistor disposed on a first pixel circuit area, a first pixel electrode disposed on a first pixel electrode area, a first color filter disposed on the first pixel circuit area while covering the first pixel transistor, and a second color filter disposed on the first pixel electrode area and the first pixel circuit area. The capping layer covers the first color filter and the second color filter, and a first opening is defined in one area of the capping layer, which overlaps the second color filter on a plane.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 4, 2021
    Inventors: Jinjoo Ha, Basrur Veidhes, Yangho Bae, Changil Tae
  • Patent number: 10998514
    Abstract: A photoelectric device includes a first photoelectric conversion layer including a heterojunction that includes a first p-type semiconductor and a first n-type semiconductor, a second photoelectric conversion layer on the first photoelectric conversion layer and including a heterojunction that includes a second p-type semiconductor and a second n-type semiconductor. A peak absorption wavelength (?max1) of the first photoelectric conversion layer and a peak absorption wavelength (?max2) of the second photoelectric conversion layer are included in a common wavelength spectrum of light that is one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, a blue wavelength spectrum of light, a near infrared wavelength spectrum of light, or an ultraviolet wavelength spectrum of light, and a light-absorption full width at half maximum (FWHM) of the second photoelectric conversion layer is narrower than an FWHM of the first photoelectric conversion layer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: May 4, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Bae Park, Takkyun Ro, Kiyohiko Tsutsumi, Chul Joon Heo, Yong Wan Jin
  • Patent number: 10991900
    Abstract: A light-emitting device includes an anode; a cathode; and an emissive layer disposed between the anode and the cathode, the emissive layer including quantum dots dispersed in a crosslinked matrix formed from one or more crosslinkable charge transport materials. A method of forming the emissive layer of a light-emitting device includes depositing a mixture including quantum dots and one or more crosslinkable charge transport materials on a layer; and subjecting at least a portion of the mixture to UV activation to form an emissive layer including quantum dots dispersed in a crosslinked matrix.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 27, 2021
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Enrico Angioni, James Andrew Robert Palles-Dimmock, Edward Andrew Boardman, Tim Michael Smeeton
  • Patent number: 10985098
    Abstract: An electronic component mounting substrate includes an insulating substrate having a rectangular shape in a plan view of the electronic component mounting substrate, the insulating substrate including a mounting portion on a principal face thereof for mounting an electronic component; and first via conductor groups each including first via conductors and second via conductor groups each including second via conductors, the first via conductors and the second via conductors penetrating through the insulating substrate in a thickness direction thereof, a number of the second via conductors being larger than that of the first via conductors, the mounting portion, the first via conductor groups, and the second via conductor groups being disposed so as not to overlap each other in a transparent plan view of the electronic component mounting substrate, the first via conductor groups being located between the mounting portion and the second via conductor groups, respectively.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 20, 2021
    Assignee: KYOCERA CORPORATION
    Inventor: Michio Imayoshi
  • Patent number: 10985084
    Abstract: Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices and silicon-based driver devices are provided. In an embodiment, an integrated circuit includes a semiconductor substrate, a plurality of transistors overlying the semiconductor substrate, and an interlayer dielectric layer overlying the plurality of transistors with a metallization layer disposed within the interlayer dielectric layer. The plurality of transistors and the metallization layer form a gate driver circuit. The integrated circuit further includes a plurality of vias disposed through the interlayer dielectric layer, a gate driver electrode coupled to the gate driver circuit, a III-V device electrode overlying and coupled to the gate driver electrode, and a III-V device overlying and coupled to the III-V device electrode.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 20, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventor: Donald Ray Disney
  • Patent number: 10985189
    Abstract: In the contact structure according to an exemplary aspect of the present disclosure and a display device including the same, the pixel may be designed regardless of the size of the contact hole by designing a size (or an area) of the contact hole to be larger than the contact area and applying different structures depending on the characteristics of the lower layer. Therefore, the size of the contact hole is increased so that the halftone mask may be easily applied and the number of masks may be advantageously reduced. Further, a degree of freedom of metal in the pixel design is increased so that the pixel may be designed in a high resolution model and the aperture ratio is increased without having the electrode margin.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 20, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: YounSub Kim, JongSik Shim, ByeongUk Gang, SeongHwan Hwang
  • Patent number: 10984938
    Abstract: The magnetoresistance effect device includes: a magnetoresistance effect element that includes a first magnetization free layer, a magnetization fixed layer or a second magnetization free layer, and a spacer layer interposed between the first magnetization free layer and the magnetization fixed layer or the second magnetization free layer; and a magnetic material part that applies a magnetic field to the magnetoresistance effect element, wherein the magnetic material part is arranged to surround an outer circumference of the magnetoresistance effect element in a plan view in a stacking direction L of the magnetoresistance effect element.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 20, 2021
    Assignee: TDK CORPORATION
    Inventors: Shinji Hara, Akimasa Kaizu
  • Patent number: 10985042
    Abstract: A SiC substrate includes a first principal surface, a second principal surface disposed on a side opposite to the first principal surface, and an outer periphery connected to the first principal surface and the second principal surface, wherein a density of composite defects present at a peripheral edge portion of the SiC substrate, in which a hollow portion and a dislocation line extending from the hollow portion are connected to each other is equal to or greater than 0.01 pieces/cm2 and equal to or less than 10 pieces/cm2.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 20, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei