Abstract: A display module is provided. The display module includes: a substrate; a thin film transistor (TFT) layer formed on one surface of the substrate; and a plurality of micro LEDs disposed on the TFT layer. The plurality of micro LEDs are transferred from a transfer substrate to the TFT layer by a laser beam radiated to the transfer substrate through openings of a mask. The openings correspond to regions in which the respective micro LEDs of the transfer substrate are arranged and the openings correspond to a width, a length, or a unit area of each of the micro LEDs.

Abstract: A semiconductor device, including: a first well of a first polarity formed in a semiconductor substrate; a source region and a drain region of a second polarity formed in the first well so as to be separated from each other by a predetermined spacing; an impurity region of the first polarity formed so as to surround the source region and the drain region; a first gate oxide film formed on the semiconductor substrate at a position between the source region and the drain region; a second gate oxide film formed on the first gate oxide film; a gate electrode formed on the second gate oxide film; and an impurity layer of the first polarity formed below the first gate oxide film.

Abstract: A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells.

Abstract: Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.

Abstract: The semiconductor structure includes a substrate; a dielectric layer formed on the substrate; an opening, formed through the dielectric layer; a contact layer formed at bottom of the opening; a blocking layer formed on a sidewall surface of the opening; and a plug formed in the opening. The plug is formed on a sidewall surface of the blocking layer and in contact with the contact layer.

Abstract: To provide a solid-state imaging element capable of further improving reliability. Provided is a solid-state imaging element including at least a first photoelectric conversion section, and a semiconductor substrate in which a second photoelectric conversion section is formed, in this order from a light incidence side, in which the first photoelectric conversion section includes at least a first electrode, a photoelectric conversion layer, a first oxide semiconductor layer, a second oxide semiconductor layer, and a second electrode in this order, and a film density of the first oxide semiconductor layer is higher than a film density of the second oxide semiconductor layer.

Abstract: A semiconductor device includes a substrate, a first GaN-based high-electron-mobility transistor (HEMT), a second GaN-based HEMT, a first interconnection, and a second interconnection is provided. The substrate has a plurality of first-type doped semiconductor regions and second-type doped semiconductor regions. The first GaN-based HEMT is disposed over the substrate to cover a first region on the first-type doped semiconductor regions and the second-type doped semiconductor regions in the substrate. The second GaN-based HEMT is disposed over the substrate to cover a second region. The first region is different from the second region. The first interconnection is disposed over and electrically connected to the substrate, forming a first interface. The second interconnection is disposed over and electrically connected to the substrate, forming a second interface. The first interface is separated from the second interface by at least two heterojunctions formed in the substrate.

Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.

Abstract: An optical sensor includes: a photosensitive layer that absorbs incident light to generate a first carrier with a first polarity and a second carrier with a second polarity different from the first polarity; a channel layer that is electrically connected to the photosensitive layer and that conducts the first carrier that has moved from the photosensitive layer; a counter electrode facing the channel layer through the photosensitive layer; an insulating layer positioned between the photosensitive layer and the counter electrode; and a source electrode and a drain electrode each electrically connected to the channel layer.

Abstract: Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.

Abstract: A thin-film transistor may include an amorphous semiconductor channel layer, an organic material piezoelectric stress gate layer formed adjacent to the amorphous semiconductor channel layer, a source electrode coupled to the organic material piezoelectric stress gate layer, a drain electrode coupled to the organic material piezoelectric stress gate layer and a gate electrode coupled to the organic material piezoelectric stress gate layer. In some embodiments, the amorphous semiconductor channel layer may be amorphous indium gallium zinc oxide. In some embodiments, the organic material piezoelectric stress gate layer may be organic polyvinylidene fluoride. In some embodiments, the amorphous semiconductor channel layer may be formed on a flexible substrate.

Abstract: An LED display screen and a manufacturing method therefor. The method comprises: presetting a temporary jig consisting of a first substrate (1) having a plurality of placement grooves, and a cover plate (3), and alternately placing R, G, and B-color LEDs in the placement grooves (2) by means of placement groove inlets (4); attaching a side cover to the temporary jig, and replacing the cover plate with an LED substrate and attaching the LEDs to the LED substrate; removing the first substrate and the side cover and sealing the LED substrate, and connecting a circuit board to the LED substrate, so as to obtain the LED display screen.

Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

Abstract: A p+ or n+ type doping process for semiconductors, allows to implement a semiconductor with a highly doped surface layer, and it comprises the steps of: providing a substrate made of semiconductor material; depositing on a surface of 5 the substrate made of semiconductor material a thin source layer made of dopant material acting as dopant source; depositing on said source layer an additional protective surface layer made of semiconductor material; inducing liquefaction of the surface layer at least until the source layer; and cooling down the substrate surface so as to obtain the diffusion of the dopant material.

Abstract: The embodiments herein relate to methods for processing a wafer through a semiconductor wafer processing system and an apparatus. According to an aspect of the present disclosure, a system for processing a semiconductor wafer is provided. The system includes a heating system, a pressure control system, and a gas flow system. The heating system is configured for heating a chuck. The pressure control system is configured for setting an internal chamber pressure. The gas flow system is configured for inflowing a gas in the process chamber to increase the internal chamber pressure to at least a base pressure. The heating system heats the chuck after the internal chamber pressure reaches the base pressure set by the pressure control system.

Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.

Abstract: A vertical storage device, a method of manufacturing the same, and an electronic apparatus including the storage device are provided. The storage device includes: a first source/drain layer located at a first height with respect to a substrate and a second source/drain layer located at a second height different from the first height; a channel layer connecting the first source/drain layer and the second source/drain layer; and a gate stack including a storage function layer, the storage function layer extending on a sidewall of the channel layer and extending in-plane from the sidewall of the channel layer onto a sidewall of the first source/drain layer and a sidewall of the second source/drain layer.

Abstract: Diode structures of stacked devices and methods of forming the same are provided. Diode structures may include a substrate, an upper semiconductor layer that is spaced apart from the substrate in a vertical direction, an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a first horizontal direction, a lower semiconductor layer that is between the substrate and the upper semiconductor layer and has a first conductivity type, a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the first horizontal direction, a first diode contact that is electrically connected to the lower semiconductor layer, and a second diode contact that is electrically connected to one of the upper semiconductor layer and a portion of the substrate. The one of the upper semiconductor layer and the portion of the substrate may have a second conductivity type.

Abstract: A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, includes a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, the growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on at least one silicon plane of [111] orientation in at least one trench, the step of forming a buffer layer being performed after the structuring step; a step of forming at least one layer of a semiconductor material of interest on the buffer layer. The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.