Patents Examined by David Vu
  • Patent number: 10867869
    Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
  • Patent number: 10868199
    Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes a capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 15, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10867934
    Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
  • Patent number: 10868180
    Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yin Lin, Teng-Chun Tsai, Po-Yu Lin
  • Patent number: 10859881
    Abstract: The present invention provides an array substrate and a method of fabricating the same, wherein the array substrate includes a base substrate, a gate layer, a gate insulating layer, a source/drain layer, a first passivation layer, a color resist layer and a second passivation layer, wherein a passivation layer via hole is provided above the source/drain layer, and gas in the color resist layer releases from a surface of the color resist layer on a side of the passivation layer via hole. The invention realizes the purpose of completely discharging the gas in the color resist layer before a cell formation process.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: December 8, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhiguang Yi
  • Patent number: 10858245
    Abstract: A semiconductor device and a method of manufacturing the same are provided such that a microelectromechanical systems (MEMS) element is protected at an early manufacturing stage. A method for protecting a MEMS element includes: providing at least one MEMS element, having a sensitive area, on a substrate; and depositing, prior to a package assembly process, a protective material over the sensitive area of the at least one MEMS element such that the sensitive area of at least one MEMS element is sealed from an external environment, where the protective material permits a sensor functionality of the at least one MEMS element.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 8, 2020
    Assignee: Infineon Technologies AG
    Inventors: Florian Brandl, Manfred Fries, Franz-Peter Kalz
  • Patent number: 10861877
    Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jun Hyoung Kim
  • Patent number: 10854811
    Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may include removing of an exposed portion of a CEM film to form an exposed sidewall region bordering a remaining unexposed portion of the CEM film under or beneath a conductive overlay. The method may further include at least partially restoring properties of the exposed sidewall region to a CEM via exposure of the exposed sidewall region to one or more gaseous annealing agents.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Paul Raymond Besser, Ming He, Jolanta Bozena Celinska
  • Patent number: 10854673
    Abstract: An elementary cell includes a non-volatile resistive random-access memory mounted in series with a volatile selector device, the memory including an upper electrode, a lower electrode and a layer made of a first active material, designated memory active layer. The selector device includes an upper electrode, a lower electrode and a layer made of a second active material, designated selector active layer. The cell includes a one-piece conductor element including a first branch having one face in contact with the lower surface of the memory active layer in order to form the lower electrode of the memory, a second branch having one face in contact with the upper surface of the selector active layer in order to form the lower electrode of the memory.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: December 1, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Gabriele Navarro
  • Patent number: 10847467
    Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Debendra Mallik, Mathew J. Manusharow, Jianyong Xie
  • Patent number: 10847736
    Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Yu-Ming Lin, Ken-Ichi Goto, Jean-Pierre Colinge, Zhiqiang Wu
  • Patent number: 10840246
    Abstract: A device includes a vertical transistor comprising a first gate in a first trench, wherein the first gate comprises a dielectric layer and a gate region over the dielectric layer, and a second gate in a second trench, a high voltage lateral transistor immediately adjacent to the vertical transistor and a low voltage lateral transistor, wherein the high voltage lateral transistor is between the vertical transistor and the low voltage lateral transistor.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
  • Patent number: 10840441
    Abstract: Techniques for MRAM patterning using a diamond-like carbon hardmask are provided. In one aspect, a method of forming an MRAM device includes: forming an MRAM stack on a substrate; depositing a metal hardmask layer on the MRAM stack; depositing a diamond-like carbon layer on the metal hardmask layer; forming a patterned resist on the diamond-like carbon layer; patterning the diamond-like carbon layer using the patterned resist to form a diamond-like carbon pillar; patterning the metal hardmask layer using the diamond-like carbon pillar to form a patterned metal hardmask; and patterning the MRAM stack into an MRAM pillar using the patterned metal hardmask to form the MRAM device. An MRAM device is also provided.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anthony Annunziata, Nathan P. Marchack, Eugene O'Sullivan, Chandrasekharan Kothandaraman
  • Patent number: 10840356
    Abstract: A method for forming a semiconductor device includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process, reshaping the first recess to form a reshaped first recess using a second etching process, wherein the second etching process etches upper portions of the fin adjacent the top of the recess more than the second etching process etches lower portions of the fin adjacent the bottom of the recess, and epitaxially growing a source/drain region in the reshaped first recess. Reshaping the first recess includes performing an oxide etch process, wherein the oxide etch process forms a porous material layer within the recess.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Rung Hsu
  • Patent number: 10840388
    Abstract: A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The superlattice may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first contact coupled to the hyper-abrupt junction region, and a second contact coupled to the substrate to define a varactor.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: November 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Patent number: 10826027
    Abstract: An organic light-emitting diode (OLED) component includes a substrate; a pixel defining layer and a plurality of first electrodes over the substrate; an insulating layer correspondingly disposed over the pixel defining layer; a first light-emitting layer over each first electrode; and a charge generation layer over the first light-emitting layer. The plurality of first electrodes are physically separated from one another by the pixel defining layer. The insulating layer is configured to facilitate manufacturing of the OLED component, such that after formation of the charge generation layer without a mask, portions thereof positionally corresponding to any two adjacent first electrodes are physically separated by the insulating layer. The OLED component can be a white light organic light-emitting diode (WOLED) component including at least one other light-emitting layer in addition to the first light-emitting layer.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: November 3, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chunjing Hu, Bin Bo
  • Patent number: 10825959
    Abstract: A display device is disclosed, wherein the display device includes a light emitting unit, including: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a protecting layer disposed on the second semiconductor layer, wherein the protecting layer includes a first position and a second position, and the first position in the protection layer is closer to the second semiconductor layer than the second position in the protection layer, wherein a first oxygen atomic percentage at the first position is less than a second oxygen atomic percentage at the second position.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: November 3, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Jia-Yuan Chen, Kuan-Feng Lee, Tsung-Han Tsai, Hsiao-Lang Lin, Jui-Jen Yueh
  • Patent number: 10818757
    Abstract: There is provided a nitride semiconductor substrate, including: a substrate configured as an n-type semiconductor substrate; and a drift layer provided on the substrate and configured as a gallium nitride layer containing donors and carbons, wherein a concentration of the donors in the drift layer is 5.0×1016/cm3 or less, and is equal to or more than a concentration of the carbons that function as acceptors in the drift layer, over an entire area of the drift layer, and a difference obtained by subtracting the concentration of the carbons that function as acceptors in the drift layer from the concentration of the donors in the drift layer, is gradually decreased from a substrate side toward a surface side of the drift layer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 27, 2020
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Yoshinobu Narita
  • Patent number: 10818603
    Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Kun Jee, Ii Hwan Kim, Un Byoung Kang
  • Patent number: 10818756
    Abstract: A technique relates to a semiconductor device. Fins are formed of varying concentrations of germanium. Gate material is formed on the fins. Source or drain (S/D) regions are adjacent to the fins, and transistor devices include the fins.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 27, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki