Abstract: A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

Abstract: Electrostatic chucks (ESCs) for plasma processing chambers, and methods of fabricating ESCs, are described. In an example, a substrate support assembly includes a ceramic bottom plate having heater elements therein. The substrate support assembly also includes a ceramic top plate having an electrode therein. A metal layer is between the ceramic top plate and the ceramic bottom plate. The ceramic top plate is in direct contact with the metal layer, and the metal layer is in direct contact with the ceramic bottom plate.

Abstract: A light emitting plate, a wiring plate and a display device are provided. The light emitting plate includes a base substrate; and light emitting units on the base substrate. Each of the light emitting units includes a light emitting sub-unit, the light emitting sub-unit includes a connection line unit and a light emitting diode chip connected with the connection line unit. The connection line unit includes at least two electrical contact pairs, and each of the at least two electrical contact pairs includes a first electrode contact and a second electrode contact; in each connection line unit, the second electrode contacts are electrically connected with each other, the first electrode contacts are electrically connected with each other, and only one of the at least two electrical contact pairs in each connection line unit is connected with the light emitting diode chip.

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

Abstract: An object of the present invention is to improve the flatness of a surface electrode without increasing the number of steps in a semiconductor device having gate structures. A method of manufacturing a semiconductor device of the present invention includes the steps of discretely forming a plurality of gate structures on a first main surface of the semiconductor substrate, discretely forming a plurality of gate interlayer films covering the plurality of gate structures of the semiconductor substrate, forming a first surface electrode being thicker than the gate interlayer films on the first main surface of the semiconductor substrate between the plurality of the gate interlayer films and on the plurality of the gate interlayer films by sputtering, and removing convex portions of concave portions and the convex portions on the first surface electrode by dry etching using photolithography, to flatten an upper surface of the first surface electrode.

Abstract: A method of forming an electrical metal contact within a semiconductor layer stack of a vertical cavity surface emitting laser includes forming a contact hole into the semiconductor layer stack. The contact hole has a bottom and a side wall extending from the bottom. The method further includes providing a photoresist mask inside the contact hole. The photoresist mask covers the side wall of the contact hole and has an opening extending to the bottom of the contact hole. The method additionally includes wet-chemical isotropic etching the bottom of the contact hole, depositing a metal on the bottom of the contact hole, and removing the photoresist mask so that the metal on the bottom of the contact hole is left as the electrical metal contact.

Abstract: A hybrid multispectral imaging sensor, characterized in that it comprises a photosensitive backside-illumination detector (DET) that is made on a substrate (100) made of InP, and that is formed of a matrix of pixels (105, P1, P2, P3) that are themselves made in a structure based on InGaAs (103), and a filter module (MF) that is formed of a matrix of elementary filters (?1, ?2, ?3) reproducing said matrix of pixels, and that is mounted into contact with said substrate (100), said substrate (100) made of InP having a thickness less than 50 ?m, and preferably less than 30 ?m.

Abstract: A photodetector for detecting deep ultra-violet light includes a substrate; first and second electrodes separated by a channel; and colloidal MnO based quantum dots formed in the channel. The colloidal MnO based quantum dots are sensitive to ultra-violet light having a wavelength lower than 300 nm.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

Abstract: A solid-state imaging element which detects visible light and ultraviolet light in one pixel provides improved resolution. First and second photoelectric conversion elements each perform photoelectric conversion of incident light. A first accumulation part accumulates electric charges that are photoelectrically converted by the first photoelectric conversion element second accumulation part is disposed on one face of a substrate and accumulates electric charges that are photoelectrically converted by the second photoelectric conversion element. A connection part is connected to the second accumulation part and transfers the electric charges accumulated in the second accumulation part to another face of the substrate.

Abstract: An electrical device includes an aluminum nitride passivation layer for a mercury cadmium telluride (Hg1-xCdxTe) (MCT) semiconductor layer of the device. The AlN passivation layer may be an un-textured amorphous-to-polycrystalline film that is deposited onto the surface of the MCT in its as-grown state, or overlying the MCT after the MCT surface has been pre-treated or partially passivated, in this way fully passivating the MCT. The AlN passivation layer may have a coefficient of thermal expansion (CTE) that closely matches the CTE of the MCT layer, thereby reducing strain at an interface to the MCT. The AlN passivation layer may be formed with a neutral inherent (residual) stress, provide mechanical rigidity, and chemical resistance to protect the MCT.

Abstract: The present disclosure relates to an image sensor structure and a manufacturing method thereof. A detection structure layer and a blind pixel structure layer are used. The detection structure layer and the blind pixel structure layer are effectively combined and further formed by ion implantation. Thus, the space ratio of a single pixel is reduced, the integration and device sensitivity are improved, and the blind pixel array and the pixel array are also in the same environment, thereby further improving the detection sensitivity and reducing the detection error.

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.

Abstract: A light-emitting diode package having a controlled beam angle is proposed. The diode package can include at least one first lead frame; at least one second lead frame formed to correspond to and be spaced apart from the at least one first lead frame; light-emitting diode chips mounted on the at least one first lead frame; a first package main body which is fixed on the partial surfaces of the at least one first lead frame and the at least one second lead frame and formed so as to have a first inclined side at a portion of the circumference around the light-emitting diode chips; and a second package main body formed so as to have a second inclined side at the remaining portion of the circumference around the light-emitting diode chips other than the portion.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer 128. The second resonator comprising a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer 128b, and in which first distance is different from the second distance.

Abstract: Transistors, and memories including such transistors, might include an active area having a first conductivity type, first and second source/drain regions in the active area and having a second conductivity type, and a plurality of control gates between the first and second source/drain regions and the second source/drain region, wherein each control gate of the plurality of control gates includes a respective first control gate portion overlying a first side of the active area, and a respective second control gate portion connected to its respective first control gate portion that is either adjacent to a second side of the active area orthogonal to the first side of the active area, or underlying a second side of the active area opposite the first side of the active area.

Abstract: A heat dissipation sheet 10 includes cohesive inorganic filler particles 1 having a breaking strength of 20 MPa or lower and a modulus of elasticity of 48 MPa or higher and a matrix resin 2.

Abstract: An apparatus includes a first semiconductor layer including a first bandgap; and a second semiconductor layer of a first polarity including a second bandgap smaller than the first bandgap and formed over the first semiconductor layer. The first semiconductor layer includes a first conductive region of the first polarity, a second conductive region of a second polarity, and a non-conductive region between the first conductive region and the second conductive region, and the second semiconductor layer is in contact with the first conductive region and the non-conductive region.

Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.