Abstract: A SiC substrate includes a first principal surface, a second principal surface disposed on a side opposite to the first principal surface, and an outer periphery connected to the first principal surface and the second principal surface, wherein a density of composite defects present at a peripheral edge portion of the SiC substrate, in which a hollow portion and a dislocation line extending from the hollow portion are connected to each other is equal to or greater than 0.01 pieces/cm2 and equal to or less than 10 pieces/cm2.
Abstract: Systems, apparatuses, and methods related to epitaxial growth on semiconductor structures are described. An apparatus may include a working surface of a substrate material and a storage node connected to an active area of an access device on the working surface. The apparatus may also include a material epitaxially grown over the storage node contact to enclose a non-solid space between the storage node contact and passing sense lines.
Abstract: A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first structure comprising a first material and a second structure comprising a second, different material longitudinally adjacent the first structure. A patterned hard mask structure is formed over the stack structure. Dielectric structures are formed within openings in the patterned hard mask structure. A photoresist structure is formed over the dielectric structures and the patterned hard mask structure. The photoresist structure, the dielectric structures, and the stack structure are subjected to a series of material removal processes to form apertures extending to different depths within the stack structure. Dielectric structures are formed over side surfaces of the stack structure within the apertures. Conductive contact structures are formed to longitudinally extend to bottoms of the apertures.
August 28, 2019
Date of Patent:
April 13, 2021
Micron Technology, Inc.
Roger W. Lindsay, Michael A. Smith, Brett D. Lowe
Abstract: Provided is a display device including: a structure including a display area and a peripheral area surrounding the display area; and an inorganic encapsulation thin film disposed on the display and peripheral areas. The peripheral area includes at least one inorganic surface portion having a closed shape continuously.
Abstract: A transparent display substrate, a manufacturing method thereof and a transparent display panel are provided. The transparent display substrate includes: a base substrate; a plurality of sub-pixels arranged on the substrate, wherein each of the plurality of sub-pixels comprising a light emitting region and a first transparent region, and the light emitting region being provided with an organic light emitting diode (OLED); a driving circuit, located in each of the plurality of sub-pixels and configured to drive the OLED to emit light, the driving circuit comprising a capacitor disposed in the first transparent region.
Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.
Abstract: A base substrate include a first substrate (110) having a first principal surface (110a) and a second principal surface (110b), and a first wiring member placed over the first or second principal surface. A pixel substrate includes a second substrate (201) having a third principal surface (201a) and a fourth principal surface (201b), a plurality of light-emitting elements (202) mounted over the third principal surface, a driver IC (205) mounted over the third principal surface, an external connection terminal mounted over the third principal surface, and a second wiring member (206) placed on the third or fourth principal surface. The driver IC drives the plurality of light-emitting elements. The external connection terminal receives an input signal that is supplied from outside the pixel substrate. The second substrate (201) is disposed to be stacked on top of the first substrate (110) so that the first principal surface and the fourth principal surface face each other.
Abstract: An opto-electronic High Electron Mobility Transistor (HEMT) may include a current channel including a two-dimensional electron gas (2DEG). The opto-electronic HEMT may further include a photoelectric bipolar transistor embedded within at least one of a source and a drain of the HEMT, the photoelectric bipolar transistor being in series with the current channel of the HEMT.
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
Abstract: A location of a center of pressure is determined in two-dimensions by a multi-layer sensor, which has a first sensing layer with a first sensing area and a second sensing layer with a second sensing area. The first sensing area includes one or more first sensing cells, and the second sensing area includes one or more second sensing cells. The first and second sensing areas overlap in plan view. Each of the first and second sensing cells can be respectively defined by a set of linearly-varying sensing aperture patterns. In each of the first and second sensing cells, a combination of the respective set of linearly-varying sensing aperture patterns forms a uniform sensing aperture pattern. The location of the center of pressure can be determined using a maximum of four output signals from the multi-layer sensor.
Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
Abstract: A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.
Abstract: The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 ?m) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 ?m and 2 ?m respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device.
Abstract: A light-emitting semiconductor chip, a light-emitting component and a method for producing a light-emitting component are disclosed. In an embodiment a light-emitting semiconductor chip includes a light-transmissive substrate having a top surface, a bottom surface opposite the top surface, a first side and a second side surface arranged opposite the first side surface, a semiconductor body arranged on the top surface of the substrate and a contacting including a first current distribution structure and a second current distribution structure, wherein the first current distribution structure and the second current distribution structure are freely accessible from a side of the semiconductor body facing away from the substrate, and wherein the semiconductor chip, on the side of the semiconductor body facing away from the substrate and on the bottom surface of the substrate, is free of any connection point configured to electrically contact the first and second current distribution structures.
Abstract: A device is disclosed. The device includes a tetragonal Heusler compound of the form Mn3-xCoxGe, wherein 0<x?1, wherein Co accounts for at least 0.4 atomic percent of the Heusler compound. The device also includes a substrate oriented in the direction (001) and of the form YMn1+d, wherein Y includes an element selected from the group consisting of Ir and Pt, and 0?d?4. The tetragonal Heusler compound and the substrate are in proximity with each other, thereby allowing spin-polarized current to pass from one through the other. In one aspect, the device also includes a multi-layered structure that is non-magnetic at room temperature. The structure includes alternating layers of Co and E. E includes at least one other element that includes Al. The composition of the structure is represented by Co1-yEy, with y being in the range from 0.45 to 0.55.
January 28, 2019
Date of Patent:
March 2, 2021
Samsung Electronics Co., Ltd., INTERNATIONAL BUSINESS MACHINES CORPORATION
Jaewoo Jeong, Mahesh G. Samant, Stuart S. P. Parkin, Yari Ferrante
Abstract: A display apparatus, comprising an element substrate including a display portion formed by arraying a plurality of organic light emitting elements on a base and a connecting portion provided on the base so as to be separated from the display portion, a driving substrate connected to the connecting portion so as to be configured to drive the display portion, and a heat-insulating portion provided between the display portion and the connecting portion in planar view in the base and configured to have lower heat conductivity than the base.
Abstract: Provided is a light-emitting diode (LED) display unit group and a display panel. The LED display unit group includes a circuit board, and a pixel unit array located on the circuit board. The pixel unit array includes a plurality of pixel units arranged in n rows and m columns, n and m are both positive integers and greater than or equal to 2. Each of the pixel units includes multiple LED light-emitting chips of at least two colors, each of the LED light-emitting chips includes an electrode A and an electrode B of opposite polarities. The LED light-emitting chip of each of the pixel units includes at least one dual-electrode chip, the dual-electrode chip has the electrode A and the electrode B located on a same side of the dual-electrode chip. All dual-electrode chips in the plurality of pixel units of a same color have connecting lines from the electrode A to the electrode B directed in a same direction.
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.
September 17, 2019
Date of Patent:
February 23, 2021
GLOBALFOUNDRIES U.S. INC.
Jinsheng Gao, Daniel Jaeger, Chih-Chiang Chang, Michael Aquilino, Patrick Carpenter, Junsic Hong, Mitchell Rutkowski, Haigou Huang, Huy Cao
Abstract: A display panel, including a light source configured to emit blue light; and a quantum dot color filter layer including: a red light converter including a red quantum dot particle configured to convert the blue light into red light, a green light converter including a green quantum dot particle configured to convert the blue light into green light, a light transmitting portion configured to transmit the blue light, and a white light generator including a first region and a second region, wherein the first region comprises a plurality of yellow quantum dot particles configured to convert the blue light into yellow light, wherein the second region transmits the blue light.
Abstract: In an embodiment, a ferroelectric memory element includes a first electrode layer, a ferroelectric structure disposed on the first electrode layer, and a second electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a ferroelectric material layer having a concentration gradient of a dopant.