Abstract: A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.

Abstract: A light-emitting element includes: a sapphire substrate having a c-plane at a main surface thereof; and a semiconductor layer provided at the main surface side of the sapphire substrate. The sapphire substrate includes a first unit including a first region, a second region, and a third region, wherein, when viewed from the main surface side, the three regions together have a shape of a regular hexagon that is evenly divided into the three regions such that each region has a shape of a rhombus; and a plurality of second units disposed to be aligned with each side of the first unit, the second unit having mirror symmetry relative to the first unit. The first unit and the second units are arranged to make a space at the center of the unit.

Abstract: A semiconductor compound structure and a method of fabricating the semiconductor compound structure using graphene or carbon nanotubes, and a semiconductor device including the semiconductor compound structure. The semiconductor compound structure includes a substrate; a buffer layer disposed on the substrate, and formed of a material including carbons having hexagonal crystal structures; and a semiconductor compound layer grown and formed on the buffer layer.

Abstract: A semiconductor sensing device that includes a nanowire conductive layer, a semiconductor sensing layer, and a conductive layer is provided. The nanowire conductive layer includes a plurality of connected conductive nanowires, and gaps are formed between the conductive nanowires. The semiconductor sensing layer is electrically connected to the nanowire conductive layer. The conductive layer is electrically connected to the semiconductor sensing layer. The semiconductor sensing layer is located between the nanowire conductive layer and the conductive layer. A manufacturing method of a semiconductor sensing device is also provided.

Abstract: A resistive random access memory device includes a first electrode made of inert material; a second electrode made of soluble material; a solid electrolyte including a region made of an oxide of a first metal element, referred to as first metal oxide doped by a second element, distinct from the first metal and able to form a second oxide, the second element being selected such that the band gap energy of the second oxide is strictly greater than the band gap energy of the first metal oxide, the atomic percentage of the second element within the region of the solid electrolyte being comprised between 5% and 20%.

Abstract: Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. Each of the 7 different pillars is immediately adjacent to six neighboring pillars. A distance to two of the six neighboring pillars is a short distance, ds; and a distance to four of the six neighboring pillars is a long distance, dl. Some embodiments include an apparatus having semiconductor pillars in a packing arrangement. The packing arrangement comprises alternating first and second rows, with pillars in the first rows being laterally offset relative to pillars in the second rows. A distance between neighboring pillars in a common row as one another is a short distance, ds, and a distance between neighboring pillars that are not in common rows as one another is a long distance, dl.

Abstract: Provided is a non-volatile memory device having a vertical channel cell. The non-volatile memory device includes a substrate having a well. A first vertical channel and a second vertical channel are in contact with the well, and protrude from the well. A pipe channel connecting the first and second vertical channels is disposed. A cut-off gate electrode stacked over the well, and surrounding side surfaces of the first and second vertical channels is disposed. A pipe gate electrode stacked over the cut-off gate electrode, and having the pipe channel is disposed. A plurality of memory-cell gate electrodes stacked over the pipe gate electrode, and surrounding the side surfaces of the first and second vertical channels is disposed. A select gate electrode stacked over the plurality of memory-cell gate electrodes, and surrounding the side surfaces of the first and second vertical channels is disposed.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a metal gate structure having curved sidewalls formed over a substrate. The semiconductor structure further includes spacers formed on the curved sidewalls of the metal gate structure. In addition, each curved sidewall of the metal gate structure has a top portion, a middle portion, and a bottom portion, and an angle between the middle portion and the bottom portion of the curved sidewall of the metal gate structure is smaller than 180° C.

Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less.

Abstract: A method of manufacturing a light-emitting device comprises the steps of: providing a substrate; forming a mask block contacting the substrate and exposing a portion of the substrate; implanting an ion into the portion of the substrate to form an ion implantation region; and forming a semiconductor stack on the substrate such that multiple cavities are formed between the semiconductor stack and the ion implantation region; wherein the mask block comprises a material made of metal or oxide.

Abstract: A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of the chip. A voltage may be applied to burn out at least one of the first fuse and the second fuse. The first critical dimension of the first fuse may result from applying a first mask to the layer and applying light having a first property to the mask. The second critical dimension of the second fuse may result from applying a second mask to the layer and applying light having a second property to the mask.

Abstract: A change in electrical characteristics can be inhibited and reliability can be improved in a semiconductor device including an oxide semiconductor. The semiconductor device including an oxide semiconductor film includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film over the oxide semiconductor film, and a third insulating film over the second insulating film. The second insulating film includes oxygen and silicon, the third insulating film includes nitrogen and silicon, and indium is included in a vicinity of an interface between the second insulating film and the third insulating film.

Abstract: A semiconductor device includes a first and second transistor. Each of the first and the second transistors includes a well of a first conductivity type, a band-shaped region provided on the well, a drain region of a second conductivity type provided on the well, and a gate electrode. The band-shaped region, the drain region and the gate electrode extend in a first direction. The band-shaped region includes a back gate region of the first conductivity type and a source region of the second conductivity type. The back gate region and the source region are arranged alternately along the first direction in the band-shaped region. A ratio of a length of the source region to a length of the back gate region along the first direction of the first transistor is greater than the ratio of the second transistor.

Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolating the first and second silicon-on-insulator region. Within a first region of the STI region, a first germanium material is deposited adjacent a first side wall of the semiconductor optical waveguide. Within a second region of the STI region, a second germanium material is deposited adjacent a second side wall of the semiconductor optical waveguide, whereby the second side wall opposes the first side wall. The first and second germanium material form an active region that evanescently receives propagating optical signals from the first and second side wall of the semiconductor optical waveguide.

Abstract: A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer and providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer. A through hole is formed to penetrate the upper package, and the upper package and lower package are electrically connected. A thermal interface material is injected into the through hole to form a first heat transmission part between, and in contact with, the upper package and the lower package.

Abstract: Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.

Abstract: Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI region in a silicon substrate, the STI region having a top width; and forming a dummy electrode on the STI region and a gate electrode on the silicon substrate, the dummy electrode having a width greater than or equal to the STI region top width.

Abstract: The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.

Abstract: A semiconductor device may include: a first semiconductor layer having a first band gap; a second semiconductor layer including first and second regions separately disposed on an upper surface of the first semiconductor layer and having a second band gap wider than the first band gap; and a third semiconductor layer disposed between the first and second regions of the second semiconductor layer, extending up to at least a portion of the first semiconductor layer. The third semiconductor layer may have a channel region doped with an impurity.