Abstract: A power line coupling and decoupling circuit for furthering peripheral system reliability. The circuit is used in a computer system which includes a host computer attached to a peripheral system via a SCSI communication interface. A light emitting diode is used as a monitor to indicate the power level on the SCSI interface. A mechanical slide switch is used to then couple or decouple a peripheral system's power source and the SCSI interface thus preventing electrical short circuits and current surges within the peripheral system. The SCSI interface receives its power directly from the peripheral power source and not from a peripheral device assembled within the peripheral system.

Abstract: A method and apparatus are disclosed for allowing at least one computer subsystem, having a central arbiter, to be interconnected with a host system also including a central arbiter. Conversion logic is added to each computer subsystem desired to be interconnected to the host. The conversion logic is positioned between the arbitration buses of the host system and the subsystem and includes two requesting arbiters, one of which arbitrates for the host system arbitration bus, and the other which arbitrates for the subsystem arbitration bus. At the default state, the conversion logic has successfully arbitrated for, and is maintaining control of the subsystem bus. After a request from a subsystem device for access to the host bus, the conversion logic arbitrates for control of the host bus. When control of the host bus is awarded to the conversion logic, control of the subsystem bus is released and the requesting subsystem device can transfer data between the subsystem and host.

Abstract: Resource master and slave combinations operating from separate local clocks asynchronously even though there may be wide speed variations among the devices, eliminating the need to synchronize the trailing edges of generated control signals with the local clock so as to free access to the resource as soon as possible without introducing timing or logic hazards.

Abstract: A method and apparatus interfaces a computer operating system with a storage volume, which is all or part of a data storage media such as a removable floppy-type disk or a hard disk. In a preferred embodiment, the method and apparatus select and associate the appropriate one of a plurality of system drivers with a respective storage volume to permit data communication between the storage volume and the operating system. The method and apparatus permit a single operating system to access a storage medium formatted in accordance with differing file systems, without reprogramming or otherwise altering the operating system. Generally, the operating system identifies which of the plurality of file system drivers is appropriate for reading a particular storage volume and, thereafter, associates the identified file system driver with the particular storage volume.

Abstract: A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a state in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep state. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.

Abstract: In an interruption circuit, each of a multiplicity of interruption generating units (12) is for generating an interruption signal upon occurrence of an interruption request. A scanning arrangement scans the units to specify one of them at a time as a particular unit and to supply the signal generated by the particular unit to a CPU (11) as a particular signal. A response supply arrangement supplies the particular unit with a response produced by the CPU upon receipt of the particular signal. Supplied with the response, the particular unit supplies the CPU with an interruption vector which is specific to each unit and makes the CPU interrupt its operation related to the particular unit. Preferably the scanning arrangement comprises a scanning circuit (16) and a first plurality of polling circuits (17), each for a second plurality of generating units with a response control circuit (27) made to correspond thereto.

Abstract: A method of routing interconnections of devices in a planar field by the use of a computer. The method effectively shortens the length of all interconnections, including interconnections which connect points on the same device, in accordance with design rules. Also, the layers constituting the planar field can be assigned weights to effectively minimize the appearance of interconnections in the layer having the highest assigned weight.

Abstract: A battery operated computer includes a battery having a plurality of serially connected banks of battery cells that are monitored during operation of the computer to detect a nearly depleted battery bank and a fully depleted battery bank. The computer also includes a plurality of microprocessors including a host or system processor, a service processor and a power subsystem processor. When a nearly depleted battery bank is detected, the power subsystem processor is interrupted and it sends a message to the service processor which in turn interrupts the host processor. An interrupt handler then powers down the system. When a fully depleted battery bank is detected, the battery is immediately disconnected and the system is shutoff to prevent polarity or cell reversal.

Abstract: A microprocessor according to the present invention comprises a sub-read bus, to which output terminals of registers of a register file of the microprocessor are coupled. The sub-read bus is in turn coupled to a main read bus of the microprocessor through a bus output circuit. Upon occurrence of a read access to any of the registers, the bus output circuit couples the sub-read bus with the main read bus, whereby data read out from the registers to the sub-read bus are transmitted to the main read bus, and under no existence of the read access, the bus output circuit interrupts the data transmission from the sub-read bus to the main read bus. With this, a load capacitance of the read bus is reduced. As a result, a time for making access to the read bus is much improved.

Abstract: A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processor or a selected set of processors. A control circuit is provided for receiving the busy signals and prohibiting storage from an external device to the registers dedicated a processor when that processor provides a busy signal.

Abstract: In a multiprocessor computer system, an access request and an access grant register is provided for storing an access request and an access grant semaphore for each shared resource. The access request and grant semaphores having a number of access request and grant bits assigned to the processors. Additionally, circuits are provided for each access request register for setting/clearing individual access request bits, and simultaneous reading of all access request bits of the stored access request semaphore. Furthermore, coordinated request and grant masks that reflect the relative access priorities of the processors are provided for the processors to use in conjunction with the current settings of the access request and grant semaphores to determine whether a shared resource is granted to a lower priority processor and whether a shared resource is being requested by a higher priority processor.

Abstract: An apparatus and method for monitoring the environment of remote components attached to a host processor by means of a standard interface bus having a limited number of address ports. The invention includes a host adapter incorporating a standard bus repeater component and an environment monitoring component. The environment monitoring component has a standard bus interface and is selectably coupled to the standard interface bus, and hence to a host processor. The host interface transceiver is coupled by means of a standard bus to the host processor, and is also selectably coupled to a drive interface transceiver by means of the standard bus. The drive interface transceiver is coupled by the standard bus to one or more storage devices. The host adapter is selectably switchable between two modes, such that either the drive interface transceiver is coupled through the host interface transceiver to the host processor, or the environment monitoring component is coupled to the host processor.

Abstract: A method and apparatus providing for data broadcasting in a two dimensional mesh of processor nodes is disclosed. In accordance with the present invention, a self-timed message routing chip is coupled to each processor node, thereby forming a two dimensional mesh of message routing chips. Broadcasting originates from a corner node, and data can broadcast through the mesh routing chips to a row, a column, or a matrix of nodes. The mesh routing chips, together, form a self-timed pipeline with each individual message routing chip having broadcasting hardware which provides for the forking of a message within that particular message routing chip. The self-timed forking of a message within individual message routing chips directly supports data broadcasting within the two dimensional mesh.

Abstract: A Buss Interface and Expansion System, which attaches to a SCSI buss provides, means for increasing the number of devices which can be attached to the buss, provides means for data compressing and decompressing data, and means for use by a host computer attached to the SCSI buss for allowing existing SCSI drives to expand their storage capacity. The disclosed system also provides means for enabling an attached drive to mirror another attached drive, means for creating virtual drives out of devices attached to the peripheral computer, and means for using RAID algorithms on groups of drives attached to the peripheral computer. The disclosed system provides the aforereferenced features while requiring only minimal modifications to the software running on a host system. Through use of electronically reprogrammable storage means, the disclosed system can be updated and reprogrammed by the host computer.

Abstract: A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining whether to run prefetch bus cycles during the execution of a conditional branch instruction. If previous bus cycles have been slow, prefetch procrastination can occurs until the branch condition resolves.

Abstract: In a multiprocessor system wherein a main storage is divided into a plurality of banks and a plurality of common buses are provided, in order to access the main storage. Each processor selects and acquires one of the buses in accordance with the utilization status of the common buses, and releases the bus after transmitting an access request utilizing the acquired bus. After processing the request, the main storage selects and acquires one of the buses in accordance with the utilization status of the common buses at that time independently of the bus which has transmitted the request, and transmits a result of the processing to the processor which has transmitted the access request utilizing the acquired bus.

Abstract: A macroservice engine is provided to exclusively carry out a sequence control in a processing of a macroservice. On the other hand, a command execution unit carries out no macroservice, but generates a bus cycle exciting request for a bus control unit, when an access request signal is generated to access a memory or peripheral registers included in a microcomputer. Thus, a processing of interruption is carried out with high speed, and a burden of a central processing unit is relieved in an interruption process.

Abstract: A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.

Abstract: In an access processing system in an information processor, the information processor includes: an access device (10, 11) for generating an access request signal; an accessed device (13) provided with a memory means (30) that is accessed by the access device (10, 11); and an address bus (14) that has the access device and accessed device connected with the information processor at least by the address bus (14).The access processing system is processed such that, if an access request is produced, when the access request signal does not require all bits in the address bus (14), an unused bit in the address bus (14) is loaded with write data to deliver it to the accessed device (13).

Abstract: A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.