Abstract: A circuit device (e.g. mounted on a printed circuit board) is connected to a data network, to which network are also connected a plurality of other circuit devices under power. On removal of such a circuit device, the output driver connecting the circuit components of the output device to the communications bus of the bus network is first disconnected from power, and only when its disconnection is stable is the device withdrawn. A control device of the circuit device is connected to the control bus of the data network, and before power is disconnected from the output driver, the control device signals to the network so as to prevent other circuit devices connected to the network from signalling on the network. Effectively, the circuit device to be removed "occupies" the bus. This occupation is maintained until the disconnection of the output driver is stable, and then the circuit device can be removed from the network.

Abstract: A multinodal system is one-way interconnected, two-way interconnected or, more generally, (n)-way interconnected, where (n) is an integer. In a one-way interconnected system, only one connection element couples any two nodes. Or, put another way, only one communication path exists between every node and every other node. A two-way interconnected system, on the other hand, has two connection elements coupling each pair of nodes. Likewise, an (n)-way interconnected system provides (n) independent connection paths between each pair. Such systems are characteristic in that the relationship between the number of independent buses (b), the number of nodes (v), the number of ports (r), and the degree of interconnectedness (n) can be expressed by the equation ##EQU1## Two-way and (n)-way interconnect arrays may be adapted for use in fault-tolerant communications.

Abstract: A queue apparatus comprises a multi-stage queue latch for storing instruction codes or data in a first-in first-out manner; a first queue pointer associated with the queue latch for indicating a read position of an upper half place portion of the instruction codes or data stored in the queue latch and a second queue pointer associated with the queue latch for indicating a reading position of a lower half place portion of the instruction codes or data stored in the queue latch. An exchanger is coupled in order to the queue latch to receive the upper and lower half place portions of the instruction codes or data read out form the queue latch and for selectively exchanging the positions of the received upper and lower half place portions.

Abstract: A method and apparatus for configuring a computer in a low-power mode are provided. In the low-power mode, dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents. Low-power mode is entered by saving an interrupt mask and by disabling interrupts, followed by saving the DMA status, finishing DMA operations, and disabling DMA. After these steps, the I/O state of the machine is saved by saving various I/O registers and ports. A refresh of the memory is forced before the system refresh operations are discontinued.

Abstract: An arbiter with first and second CPU timers is provided which advantageously allows measuring and controlling CPU bus ownership intervals via the arbiter. The first CPU timer, a running timer, specifies the total interval that the CPU is allocated the bus. The second time, an idle timer, specifies an interval which the CPU may own the bus without performing an operation. The arbiter uses these two timers to dynamically adjust and control CPU bus ownership.

Abstract: A computer system manages storage of files and/or directories. The computer system stores a specification of a file space allocation for an application support processor, an application program, or a group of application programs. The computer system can store temporary files for the application support processor, application program or group of application programs that require greater file space than the file space allocation. This is done by temporarily providing extra unused file space during processing of the temporary files. When the application support processor, application program or group of application programs attempts to commit the files, the file space allocation is enforced. The computer system can store specifications of file space allocations for a plurality of other application support processors, application programs or groups of application programs.

Abstract: This invention is a data processing device operated by a power source and includes a clock signal generator section for generating a clock signal whose clock frequency is changed according to a to-be-measured voltage, a counter section for counting the clock signal generated from the clock signal generator section in a preset period of time, a comparator section for comparing the count of the counter section with a reference value, and a voltage detector section for deriving the to-be-measured voltage based on the result of comparison by the comparator section. Variation in the power source voltage of the data processing device can be detected by use of a voltage detection circuit having the above sections and formed in a simple and small-sized construction.

Abstract: A computing system has a wireless interface, for example an infrared interface. The infrared interface is used to directly transmit configuration information to and/or receive configuration from a configuration storage device without going through the standard I/O interfaces of the computing system. This is done by connecting the infrared interface directly to the configuration storage device. Alternately, the infrared interface is used to allow direct connection to a memory bus without using an I/O bus. This allows the computing system to send out diagnostic information without using the I/O bus. The infrared interface can be full duplex allowing requests for diagnostic information to be made by a handheld computing system such as a handheld computer or a calculator. The infrared interface may also be used to download data and programming code to a handheld computing system and for receiving data from the handheld computing system.

Abstract: A microcomputer that comprises a standby signal generating circuit for supplying a standby signal to a processor and an initial reset circuit for supplying an initial reset signal to the processor when supply voltage becomes lower than a predetermined value, wherein the standby signal is produced in either case where a standby condition is sustained or imposed to switch the processor from an operation mode to a standby mode so that the supply voltage may be lowered during the standby mode, is characterized by the provision of a blocking circuit for blocking the entrance of the initial reset signal into the processor according to the standby signal thus produced.

Abstract: A computer system uses microcode subroutines to execute complex macroinstructions. Each macroinstruction is used to index a table. Simple macroinstructions have a single microinstruction counterpart in the table, and such microinstruction is performed directly in order to execute that macroinstruction. The table entry corresponding to more complex macroinstructions is a jump microinstruction, with the target of the microcode jump being an appropriate subroutine in microcode memory.

Abstract: A PLC (programmable logic controller) processor which carries out logical operations. The processor comprises a logical operation unit (2) for executing a logical operation, a jump inhibition unit (3), a jump condition checking unit (4) for checking whether or not a jump can be carried out while omitting executions of subsequent instructions, and a jump instruction execution unit (5) for executing the jump instruction. When the result of the checking by the jump condition checking means (4) indicates that subsequent instructions need not be executed and the jump should be carried out, the jump instruction execution means executes the jump, whereby unnecessary instructions are not executed, thus the speed of the logical processing is increased.

Abstract: A system for use in conjunction with a digital data processing system includes an applications program, a user interface and a hierarchy information management system. The applications program generates an information hierarchy including a plurality of hierarchy information items organized in a plurality of hierarchy levels. The user interface includes a display for displaying information to a user and an event initiator, such as, for example, a keyboard or a mouse for generating event information. The hierarchy information management system receives hierarchy information items at selected hierarchy levels from the applications program and transmits the received hierarchy information items to the display of the user interface for display, and responds to the event information by initiating selected operations in connection with the received hierarchy information.

Abstract: A variable length cache system keeps track of the amount of available space on an output device. The capacity of the cache system is continuously increased so long as it is less than the available output space on the output unit. Once the size of the cache system exceeds the available output space on the output unit, which is less than the total space available on the output unit by a predetermined amount, the contents of the cache memory are flushed or written to the output device and the size of the cache memory is reduced to zero.

Abstract: The present invention is a method for a microprocessor such that when a call is made to a subroutine or an interrupt, a return address is stored in a "stack" memory (RAM) and also that a particular piece of hardware write the return address to an additional register (latches) within the microprocessor. The method enables a comparison to be made at the end of the subroutine or interrupt such that the address to which the subroutine tries to return is compared to the address as latched into the hardware portion of the microprocessor to detect whether any human error has occurred in the programming of the interrupt program or the subroutine.

Abstract: Each time a programmable read only memory is written, the memory device of the programmable read only memory is degraded a certain extent.This invention relates to a microcomputer having a programmable read only memory. The programmable read only memory includes a special area for recording the number of writes to a user operating area and for monitoring the life of the programmable read only memory.

Abstract: There is disclosed a low-power consuming information processing apparatus having a storage unit for storing an application program of a main task, a main CPU capable of operating at a high speed for executing the application program, a sub-CPU for executing a process other than the main task, the sub-CPU being of a low-voltage, low-power consuming type, and a peripheral circuit being controlled by the sub-CPU.

Abstract: A system permitting configuring of its total memory space includes a processor, an external operating device having a first address space and a bus coupling said central processing unit and the operating device. A starting address for the total memory space is defined and the operating device calculates its own starting address from the starting address of the total space.

Abstract: An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The apparatus comprises a local processing unit which is configured substantially the same as the host processing unit and is driven by a separate local program distinct from the host processing program driving the host processing unit. The apparatus further comprises a supplemental processing circuit for processing information, which supplemental processing circuit is responsive to the host processing unit and to the local processing unit to determine whether the host processing unit or the local processing unit has operative access to the first data bus. In its preferred embodiment, the first data bus and the second data bus are operatively connected by a configurable buffer circuit for effecting data bus connection.

Abstract: A mass data storage unit includes a plurality of first data storage modules that form a mass information storage library, a data directory archive for maintaining a directory of the information contained on each data storage module, and data record/playback modules for receiving any selected data storage module in the mass storage library. A plurality of interface computers are coupled to a plurality of host computers for receiving data and for generating request signals to access information stored in the mass storage library. A file directory is coupled to the interface computers and the data directory archive for receiving the request signals, locating in the data directory archive the address containing the stored information and generating a data address location output signal for the stored information.

Abstract: A plurality of processors are connected to the interprocessor communications facility in the multiprocessing system of the invention. The interprocessor communications facility has arbitration circuitry, mailbox circuitry, and processor interrupt circuitry. The interprocessor communications facility of the invention is centralized and does not require the use of main storage. This enables processors to communicate with each other in a fast and efficient manner. The arbitration circuitry prevents simultaneous access of the interprocessor communications facility by more than one processor, and decodes the commands sent from the processors and routes them to the processor interrupt circuitry or to the mailbox circuitry, depending on the command. The mailbox circuitry of the invention receives messages from sending processors and provides them to the intended receiving processors in a safe and secure manner.