Abstract: Disclosed is a bus expansion unit for extending the bus of a computer system which has an asynchronous bus cycle. The bus expansion unit includes an asynchronous state machine which uses a delay line to determine some of its states. The bus expansion unit recognizes the address and bus status and holds or latches a select signal. In addition, the bus expansion unit delays the -CMD signal until the peripheral has the opportunity to place valid data on a bus channel. In addition, the bus expansion unit includes an arbitration circuit for the peripheral attached thereto.

Abstract: Two identical CRC circuits are cross coupled to make alternate CRC calculations based on the other CRC circuit's calculation. Throughput of the CRC code calculation is improved by applying alternate input data simultaneously at each of the CRC circuits so that when one calculation is completed the next input data is available to immediately begin the next calculation. The output of each CRC circuit is fed into one of two latches that make up an LSSD register such that the first latch captures the first CRC calculation on a first clock of non-overlapping clocks. The second CRC calculation is captured by the second latch on a second clock of the non-overlapping clocks. Two CRC calculations can be made in one period of the non-overlapping clocks while avoiding race problems.

Abstract: In transformation from a symbol string to a term, transformation rules received describe structures of input symbol strings in the form of a context-free grammar, and include structures of output terms as arguments of terminal symbols and non-terminal symbols. An inputted symbol string is analyzed by reduction processing based on the structures of input symbol strings described in the transformation rules, and an intermediate tree is formed. A term for output is produced in accordance with the structures of output terms shown in the arguments of the terminal symbols and the non-terminal symbols corresponding to the structure of the inputted symbol string. Transformation of structured data is performed in like manner using transformation rules which describe structures of input data in terms of relations between classes of partial structures, and includes structures of output data as arguments of class identifiers.

Abstract: System for providing self-selection arbitration among a plurality of slave processors connected to a VME back plane. The slave processors are connected to a common ID bus, interrupt line, and acknowledge bus. Slave processors contend for access to the VME back plane by asserting an interrupt level unique to a group of slave processors on the interrupt line. Simultaneously, the contending slave processors apply their respective addresses to the ID bus. When a contending slave processor receives an acknowledge over the acknowledge bus from a master processor, and senses its own address on the ID bus, it has successfully won the right to transmit data over the data bus.

Abstract: A method for placing a multi-car train with a communication network in an energy saving layup mode, the communication network having a master node interconnected to at least one other node via a train bus, the train having a head car for carrying the master node and at least one other car for carrying the at least one other node with an intelligent subsystem unit coupled to the train bus by the other node. The method includes transmitting a shutdown signal to the master node; sending in response to the shutdown signal a shutdown message from the master node to the at least one other node after a predetermined amount of time; and shutting down power to the intelligent subsystem unit in response to receiving the shutdown message at the at least one other node.

Abstract: An interface (12) is disclosed for coupling a peripheral device (18) to the serial port (14) of a computer (16). In one application, the interface allows the serial port to provide the power required by a scanner for operation. To reduce power consumption, the scanner is typically operated in either a reduced-power, nonscanning mode or a higher power scanning mode. The interface may include an energy storage device (36) for storing energy from the serial port when the scanner is operated in the nonscanning mode and providing energy to the scanner when it is operated in the scanning mode. Thus, a scanner that requires more power than the serial port can provide at any one time can be used. The interface also includes a shutdown circuit (46) that prevents the scanner from being operated in conditions that might lead to the erroneous interpretation of data. Further, an input leakage isolation circuit (48) is included to prevent the discharge of the storage device when the scanner is not in use.

Abstract: A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.

Abstract: A controller for controlling requests to memory, said requests involving executing in a computer system an instruction having a variable length operand, for use in a computer system for managing the main store in a page size of 2.sup.m byte units by on demand paring processing and for executing an instruction or an operation in not larger than 2.sup.m (n is larger than m) byte operand units includes a detector for detecting the presence of operand data on a same or single page by referencing the (n-m) most significant bits of the n least significant bits of an effective address which has been generated. If the detector has detected the presence of the operand data on the same page, the memory request is altered by dispensing with an unnecessary check request.

Abstract: A distributed arbitration scheme for a communications bus wherein the bus interface modules decide among themselves who should next use the bus. The protocol is a common multiprocessor backplane bus interface for supporting multiprocessing, shared memory, and memory mapped input/output operations. The protocol allows programmable priority which can be changed during system operation. The architecture handles interrupts over the bus and therefore eliminates separate interrupt lines. The scheme can implemented in CMOS technology and is compatible with other integrate circuit device technology.

Abstract: A module interfaces a programmable controller to several serial communication networks for the exchange of data carrying messages. A central processor controls the transfer of data between the module and other programmable controller components. The module has a separate port circuit for each of the networks permitting communication using different protocols. Messages received through one port circuit can be routed to another port circuit or other programmable controller components as specified by routing data stored in the module. The module also can be configured to detect when a given sequence of data is contained in a received message or to parse a section of data from the message. In these cases, an indication of whether the data sequence was found or the parsed data is routed to a designated output of the module.

Abstract: Disclosed is a switch that allows a peripheral device, such as a printer, to be shared by multiple computer systems. The switch connects to each of the computer systems, and also to the peripheral device being shared. The switch stores the current state of the peripheral device for each to the computer systems, so that when a particular system requests access to the peripheral device, the switch can restore the state of the peripheral device to the last state established by the system requesting usage. Therefore, the system requesting usage need not know that other systems may have used the peripheral device in the interim.

Abstract: Method and apparatus for time-shared processing of a sequence of principal data words having a constant period and at least one secondary word of a second sequence of secondary data words such that there is continuous processing of the secondary data word among said principal data words is formed. A principal data word becomes available for processing at each constant period, and the processing time of such a principal data word is less than that period. After a predetermined number of principal data words first becomes available for processing, the processor begins processing each of the available principal data words such that the next principal data word of the sequence begins processing immediately after processing of the previous principal data word of the sequence is complete.

Abstract: In a microcomputer having two program execution states including a supervisor state and a user state, there is disposed a flag or a register having such a flag indicating whether or not a RAM area used in the supervisor state can be used in the user state by the CPU. A judge circuit determines whether or not the CPU has made an attempt to invalidly access the RAM in the user state based on the content of the flag or the register and that of the supervisor/user state specify bit in the status register. In a case of an occurrence of an access violation, a violation signal is sent to the CPU and the selection signal of the RAM is disabled (to be set to an ineffective state), thereby increasing the reliability of the system.

Abstract: A microprocessor provides a bus state referred to as "loop-back". This state holds the data bus at valid logic levels, without use of resistors, after a read transaction has been completed and there are no pending bus transactions. When this state is entered, the data just read from the data bus is driven back onto the data bus, and the device which had provided the data is placed in the tri-state (high-impedance) condition. This loop-back feature, combined with the fact that all other outputs are held at their previous values, provides for near-zero power dissipation on the bus. The inventive technique avoids the use of pull-up resistors, which are provided on prior art tri-state busses to ensure that the busses do not float and enter the threshold region where high power dissipation occurs.

Abstract: Methodology and circuitry for providing adaptable dynamic prioritization of a plurality of requestors for a shared resource with a plurality of prioritization commands selected according to the winning request of each arbitrage operation.

Abstract: A data bus has a bit length of 2 words, and is divided into two bit groups, each of which corresponds to one word. Therefore, the data bus can simultaneously transfer data of two words. A register, a data operation part of a CPU, a RAM and a ROM is connected to the data bus. Even if there is generated data of two words to be transferred in these registers, the data operation part, the RAM and the ROM, the data bus can simultaneously transfer the data. In order to prevent conflict of data on the data bus, there are provided a bus driver, a multiplexer and a bus selector.

Abstract: A system includes a computer main body, and an expansion unit detachably connected to the computer main body, for supplying a power to the computer main body and expanding a function of the computer. A power in the expansion unit is consumed in the expansion unit prior to power supply to the computer main body so as to stably supply a power to circuit components of the expansion unit. The expansion unit includes an expansion connector to which at least one expansion board is arbitrarily detachably connected, a power supply for supplying the power to the circuit components including the expansion circuit boards and to the computer main body, and a switch for detecting a power supplied from the power supply to the circuit components and stopping power supply to the computer main body by the power supply when the power exceeds a predetermined value.

Abstract: A communication system including one or more host adapters connected to a host computer, each adapter having multiple serial communication ports for transferring data between the computer and several TTY devices. Several of the adapter's serial ports include a high speed serial link for communicating with a data concentrator. The adapter automatically detects the presence of a concentrator connected to a switchable port and switches to the high speed link. Each concentrator includes multiple serial ports for communicating with TTY devices, and a high speed serial link for communicating with the adapter's high speed link. The concentrators allow more than one TTY device to share a single adapter serial port. Data from all of the TTY devices is accumulated into an adapter data buffer during a configurable time period or until a certain amount of data is accumulated, at which time the adapter interrupts the computer and transfers the accumulated data to the computer in one transfer operation.

Abstract: In a computer system where maximum allowable latency periods are established for each of eight agents to access a shared buffer, the invention provides a timed loop that prevents starving out of any agent and a dynamically variable loop to prevent an allocation of time for an access to the shared buffer by an idle agent to reduce latency wherever possible.

Abstract: A data buffering device having a data buffer permitting data storage in a first storage area A while the area A is advanced over a predetermined number of storage areas of the buffer in a predetermined sequence and permitting data reading from a second storage area B while the area B is advanced in the same sequence; a first device judging whether or not it is permissible to carry out at least one of a simple data storage and a simple data reading; a second device executing, if the judgement of the first device is negative, a return judgement whether or not it is necessary to return a corresponding one, or each, of the areas A and B to a leading storage area of the buffer, and a possibility judgement whether or not the buffer has at least a predetermined number of storage area or areas permitting a corresponding one, or each, of a data storage and a data reading, if the possibility judgement is affirmative the second device placing the first device in a condition in which the first device provides an affirmat