Abstract: An electrostatic discharge circuit includes six transistors. A power supply voltage node is coupled with a gate and a drain of a first transistor and connected to a source of a second transistor and a drain of a fifth transistor. A source of the first transistor is coupled to a ground voltage node and connected to a gate of a third transistor and a gate of a fourth transistor. A gate of the second transistor is connected to the drain of the first transistor. A source of the third transistor is connected to the drain of the second transistor and a gate of the fifth transistor. A drain of the fourth transistor is connected to a drain of the third transistor. A source of the fourth transistor and a source of the sixth transistor are connected to the ground voltage node.

Abstract: An apparatus for detecting an open neutral condition in a split phase power system is described. The apparatus includes two powered lines providing output electricity to an electrical distribution system and a shared neutral line providing a grounded neutral to the first and second powered lines. The apparatus is configured for detecting when an open neutral condition is present in the split phase power system by determining when a power current is present on one or both of the first and second powered lines while a return current is not present on the neutral line; and in response to detecting that the open neutral condition is present, causing an interrupter to interrupt the power supplied by the first and second powered lines or to generate a signal indicating an open condition.

Abstract: An input output circuit and an electrostatic discharge (ESD) protection circuit are provided. The ESD protection circuit is adapted to a charged-device model (CDM). The ESD protection circuit includes a bipolar junction transistor (BJT). The BJT has a first end coupled to an input end of an input buffer and an output end of an output buffer. A second end of the BJT is coupled to a first ground rail. A control end of the BJT is coupled to one of a first power rail, a second power rail, the first ground rail and a second ground rail.

Abstract: Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.

Abstract: A crowbar module includes first and second electrical terminals, a module housing, and first and second crowbar units. The first crowbar unit is disposed in the module housing and includes a first thyristor electrically connected between the first and second electrical terminals. The second crowbar unit is disposed in the module housing and includes a second thyristor electrically connected between the first and second electrical terminals in electrical parallel with the first crowbar unit.

Abstract: An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.

Abstract: A method and an apparatus for use in an earth-fault protection in a three-phase electric network, the apparatus is configured to detect a phase-to-earth fault in the network, to determine for each of the phases of the network a phase current during the fault or a change in the phase current due to the fault, to detect a faulted phase of the network, to determine an estimate of an earth-fault current on the basis of the faulted phase and the phase currents or the changes in the phase currents, to determine a zero-sequence voltage of the electric network or a change in the zero-sequence voltage, and to determine a direction of the phase-to-earth fault from the measuring point on the basis of the estimate of the earth-fault current and the zero-sequence voltage or the change in the zero-sequence voltage.

Abstract: A substrate fixing device includes a base plate including therein a gas supply section, and an electrostatic chuck provided on the base plate. The electrostatic chuck includes a base having a mounting surface on which a target to be held by electrostatic attraction is mounted, an insertion hole, penetrating the base, having an inner surface that defines the insertion hole and is threaded to form a female thread, and a screw member, having an outer surface that is threaded to form a male thread, and inserted into the insertion hole to assume a mated state in which the male thread mates with the female thread. A gas from the gas supply section is supplied to the mounting surface via the screw member.

Abstract: A device for ionising air includes a case, in which there are a blower, which includes a rotor to generate a pulsed airflow and an exhaust pipe to channel this flow; a device for producing ions, which includes a high-voltage electrical generator; an electrode connected to the generator and of which one free end, formed of a cluster of filaments made of conductive material, extends to the right of the exhaust pipe to release ions there by corona discharge. The device further includes a diffuser provided with a pipe which, in the extension of the exhaust pipe, delimits a compression chamber, with an expander which extends the pipe and includes a series of channels which extend form an inner face of the expander to an opposite outer face.

Abstract: An active two-terminal inductor device with a controllable inducitance based on an inductance value input L_I. A processor system PRS executes an algorithm which controls a power converter PCV with controllable electric switches connected to the two external terminals A, B along with a fixed value inductor component L1. Based on sampling of at least a voltage or a current in connection with the inductor component L1, the algorithm controls the power converter PCV to provide a resulting inductance across the external terminals A, B which serves to match the inductance value input L_I.

Abstract: A substrate processing apparatus includes a stage including a first section and a second section, pins, a lifter configured to raise and lower the pins, and a controller configured to control the lifter. On the first section, a substrate is placed. On the second section, an edge ring is placed. The second section is provided at a periphery of the first section. Also, at the second section, holes are provided. The pins are provided in the respective holes so as to move up and down through the holes.

Abstract: Embodiments disclosed herein may include a heater pedestal. In an embodiment, the heater pedestal may comprise a heater pedestal body and a conductive mesh embedded in the heater pedestal. In an embodiment, the conductive mesh is electrically coupled to a voltage source In an embodiment, the heater pedestal may further comprise a support surface on the heater pedestal body. In an embodiment, the support surface comprises a plurality of pillars extending out from the heater pedestal body and arranged in concentric rings. In an embodiment pillars in an outermost concentric ring have a height that is greater than a height of pillars in an innermost concentric ring.

Abstract: The electronic circuit protector of the invention comprises a first semiconductor, a second semiconductor, a third semiconductor, a first diode, a second diode, a first resistor, a second resistor and a third resistor, constituting an application circuit with load overload or short circuit protection function, which avoids the damage caused by overload or short circuit at both terminals of the load.

Abstract: The present invention discloses an electrostatic discharge protection circuit having time-extended discharging mechanism. A RC circuit is coupled between an ESD input terminal that receives an ESD input and a ground terminal and includes an input control terminal. An inverter includes a P-type transistor coupled between the ESD input terminal and an output control terminal and an N-type transistor circuit including N-type transistors coupled in series and between the output control terminal and a ground terminal, wherein two of the N-type transistors has an internal connection terminal. Gates of the P-type transistor and N-type transistors are controlled by the input control terminal. A switch transistor is coupled between the ESD input terminal and the internal connection terminal. A discharging transistor is coupled between the ESD input terminal and the ground terminal. The gates of the switch transistor and the discharging transistor are controlled by the output control terminal.

Abstract: Implementations described herein provide a substrate support assembly. The substrate support assembly has a first ceramic plate having a workpiece supporting surface and a bottom surface. The first ceramic plate has a plurality of secondary heaters each forming a plurality of micro zones. The substrate support assembly has a second ceramic plate having an upper surface and a lower surface. A first metal bonding layer is disposed between the bottom surface of the first ceramic plate and the upper surface of the second ceramic plate. A third ceramic plate has a top portion and a bottom portion. The third ceramic plate has primary heaters. A second metal bonding layer is disposed between the lower surface of the second ceramic plate and the top portion of the third ceramic plate.

Abstract: A multilayer coil component 1 includes an element body 2 having a plurality of stacked insulator layers 6 and having an outer surface provided with recessed portions 7 and 8, a coil 9 disposed in the element body 2, and terminal electrodes 4 and 5 connected to the coil 9 and disposed in the recessed portions 7 and 8. The recessed portions 7 and 8 are defined by a bottom surface and a side surface extending in a depth direction of the recessed portions 7 and 8 over the outer surface and the bottom surface, the terminal electrodes 4 and 5 have a first surface facing the bottom surface and a second surface facing the side surface, and a connection region A where a compound of elements constituting the element body 2 and a metal component are mixed is exposed to the second surface.

Abstract: An arrangement contains a polyphase transformer which has primary windings and secondary windings. The secondary windings are connected to form a star circuit, the star point of which is connected to earth potential by means of an overvoltage-limiting device. The overvoltage-limiting device has a first overvoltage-limiting component. A switch, which electrically bridges the first overvoltage-limiting component in its closed state, is assigned to the first overvoltage-limiting component.

Abstract: Disclosed is a device for controlling a terminal connected in a multi-terminal high-voltage direct current transmission facility, the terminal being able to provide or draw power on the DC part of the facility comprised between an upper power limit and a lower power limit, the device further comprising at least one regulation circuit configured to vary the power provided or drawn by the terminal on the DC part of the facility, as a function of a voltage variation on the DC part of the facility, the device further comprising a limitation circuit configured to limit the variation of the power provided or drawn by the terminal, for a given voltage variation, when the power difference between the power provided or drawn by said terminal and the upper power limit or the lower power limit becomes smaller than a determined value.

Abstract: A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

Abstract: A discharging method of removing electric charge from a substrate is provided. In the discharging method, gas is supplied into a processing chamber while the substrate is placed on an electrostatic chuck provided in the processing chamber, and direct-current (DC) voltage is applied to an attracting electrode of the electrostatic chuck, until discharge occurs in the processing chamber. After the discharge occurs, the DC voltage is adjusted to a magnitude in which an amount of charge on the substrate becomes zero or becomes in a neighborhood of zero, and the substrate is removed from the electrostatic chuck.