Patents Examined by Dharti H. Patel
  • Multiple trigger electrostatic discharge (ESD) protection device for integrated circuits with multiple power supply domains
    Patent number: 11611211
    Abstract: A system having a device for conducting an electrostatic discharge (ESD) current from a designated pin node. The system includes first and second pin nodes, and a switching device having a first switching threshold. The switching device includes a first, terminal coupled to a reference node, and a second terminal, coupled to the first pin node to actuate the switching device to conduct ESD current from the first pin node responsive to a voltage between the first pin node and the reference node exceeding the first switching threshold. The switching device further includes a third terminal, coupled to the second pin node, to actuate the switching device to conduct ESD current from the first pin node responsive to a voltage between the first pin node and the second pin node exceeding a second switching threshold.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: March 21, 2023
    Assignee: Analog Devices, Inc.
    Inventor: Michael Amato
  • Fault protection device with ground trip delay and method
    Patent number: 11611204
    Abstract: A reclosing fault protection device detects a partial bypass state. Upon detecting the partial bypass state, the fault protection device implements a ground trip delay operating state. The ground trip delay operating state provides a delayed ground trip response characteristic.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: March 21, 2023
    Assignee: S&C Electric Company
    Inventors: Christopher McCarthy, Raymond P. O'Leary
  • ESD circuit with current leakage compensation
    Patent number: 11605626
    Abstract: An ESD protection circuit includes a trigger transistor that is responsive to a detection signal indicating an ESD event. The trigger transistor pulls the voltage of a hold node towards a voltage of a power supply rail in response to the detection signal indicating an ESD event. The ESD protection circuit includes a replica trigger transistor whose leakage current controls current provided to the hold node after the detection signal no longer indicates an ESD event to compensate for leakage current through the trigger transistor.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: March 14, 2023
    Assignee: NXP B.V.
    Inventors: Jian Gao, Marcin Grad
  • EMI filter for DC motor
    Patent number: 11606008
    Abstract: An electromagnetic interference (EMI) filter 32 is provided which is suitable for a DC motor 10. The EMI filter 32 comprises an EMI suppression circuit 34 having first and second DC-motor-terminal inputs 36a, 36b, and an MW-band power choke 44 coupled to one of the first and second DC-motor-terminal inputs 36a, 36b to increase the motor inductance in the MW frequency band.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 14, 2023
    Assignee: JOHNSON ELECTRIC INTERNATIONAL AG
    Inventor: Bo Hu
  • Switch chip with bond wires replacing traces in a die
    Patent number: 11600612
    Abstract: A switch chip includes a first switch device, a first ESD protection device and a second ESD protection device. The first switch device is electrically coupled between a first pad and a second pad. The first ESD protection device is electrically coupled to a third pad which is electrically coupled to the first pad by a first bond wire. The second ESD protection device is electrically coupled to a fourth pad which is electrically coupled to the second pad by a second bond wire.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: March 7, 2023
    Assignee: VIA LABS, INC.
    Inventors: Didmin Shih, Tengyi Huang, Ting-Yen Wang, Yen Wei Wu
  • Semiconductor protection circuit
    Patent number: 11600993
    Abstract: According to one embodiment, a semiconductor protection circuit includes a first MOS transistor that has a drain that is connected to an input terminal, a source that is connected to an output terminal, and a gate that is connected to a control terminal, a second MOS transistor that has a drain that is connected to the gate of the first MOS transistor and a source that is connected to the source of the first MOS transistor, a rectifier element that is connected in a forward direction from a gate of the second MOS transistor to the gate of the first MOS transistor, and a low-pass filter that is connected between the gate and the source of the second MOS transistor.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 7, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Chen Kong Teh
  • Wireless monitoring of electrical connector
    Patent number: 11594847
    Abstract: An electrical connector includes a male electrical plug, a female socket, a housing, and a control system. The male electrical plug, which is supplied with power, is electrically connected to the female socket. The housing contains the male electrical plug, the female socket, and a control system. The control system includes a temperature sensor and a transceiver with the temperature sensor sensing a temperature at a location within the housing and the transceiver transmitting a signal representative of the temperature to an alarm device remotely located from the electrical connector. The electrical connector can include one or more switches that are remotely controllable by the alarm device to interrupt the electrical connection between the male plug and the female socket.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 28, 2023
    Inventor: Kevin O'Rourke
  • System and method for ESD protection
    Patent number: 11594878
    Abstract: In accordance with an embodiment, a method for protecting a circuit includes: receiving a stress caused by an electrostatic discharge (ESD) event from a first node; limiting a current using a current limiting element coupled between the first node and a second node connected to the circuit; and limiting a voltage on the second node caused by the ESD event using a protection circuit including at least one MOS transistor having a load path coupled to the second node, where the at least one MOS transistor is disposed in a well, and a bias circuit coupled to a gate and a bulk connection of the at least one MOS transistor and a supply node.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: February 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Adrien Benoit Ille, Claudia Kupfer, Gernot Langguth
  • Ground fault interrupt and USB power supply electrical wiring device
    Patent number: 11588326
    Abstract: An electrical wiring device including a ground fault interrupt assembly, the ground fault interrupt assembly comprising a ground fault interrupt circuit, being formed on a first printed circuit board, and a trip mechanism, the ground fault interrupt circuit being configured to detect a differential current between the line conductor and the neutral conductor and to trigger the trip mechanism to electrically decouple the plurality of line terminals from the plurality of load terminals, according to a predetermined criterion, based, at least in part, on the different current; and a USB power supply circuit being formed on a second printed circuit board disposed within the compartment, the USB power supply circuit providing to the at least one USB port, wherein the first printed circuit board and the second printed circuit board are separated by a distance within the inner compartment.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: February 21, 2023
    Assignee: PASS & SEYMOUR, INC.
    Inventors: Clayton Roberts, Jeffrey C. Richards, Kristopher E. Glassford
  • Kitchen appliance assembly and method of converting a kitchen having one of a slide-in and drop-in appliance to a kitchen having built-in appliances
    Patent number: 11585539
    Abstract: There is provided a method of converting a kitchen having one of the slide-in and the drop-in appliance electrically coupled to a range receptacle, to a kitchen having built-in appliances. The method includes removing the one of the slide-in and the drop-in appliance from the range receptacle. The method includes installing at least two kitchen appliances into at least one of preexisting countertops and cabinetry of the kitchen. Each of the kitchen appliances includes a range plug. The method includes providing a power strip apparatus comprising a range plug and a power strip having a plurality of range sockets electrically coupled to the range plug of the power strip apparatus. The method includes inserting the range plug of the power strip apparatus into the range receptacle and inserting the range plugs of the kitchen appliances into respective ones of the range sockets of the power strip.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: February 21, 2023
    Assignee: Regius Investment Corp.
    Inventor: Robert Alan Boykiw
  • Combined positive and negative voltage electrostatic discharge (ESD) protection clamp with cascoded circuitry
    Patent number: 11581729
    Abstract: A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: February 14, 2023
    Assignee: Cypress Semiconductor Corporation
    Inventors: David Michael Rogers, Henry H. Yuan, Mimi Qian, Myeongseok Lee, Sungkwon Lee, Yan Yi, Ravindra M. Kapre, Murtuza Lilamwala
  • Overvoltage protection circuit for a PMOS based switch
    Patent number: 11575254
    Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 7, 2023
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Manoj Kumar, Ravinder Kumar, Nicolas Demange
  • Interface circuit with robust electrostatic discharge
    Patent number: 11575259
    Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 7, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Wen-Yi Chen, Reza Jalilizeinali, Sreeker Dundigal, Krishna Chaitanya Chillara, Gregory Lynch
  • Systems and methods for radio frequency hazard protection for external load connections
    Patent number: 11563458
    Abstract: Systems and methods for RF hazard protection are provided. In one embodiment, a RF protection coupler comprises: a first port to couple to an output of an RF source circuit; a second port to couple to an external RF load; a source side and load side RF switches, wherein the source side RF switch and the load side RF switch are each switch between a first and second states in response to a detected matting. In the first state the source and load side RF switches establish an electrical path between the first and second ports. In the second state: the source side RF switch couples the first port to an impedance load that is impedance matched to the output of the RF source circuit; the load side RF switch couples the second port to an electrical ground; and a gap between the switches electrically isolates the ports.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 24, 2023
    Assignee: CommScope Technologies LLC
    Inventors: Karl-Heinz Fackler, Rainer Friedrich, Anand Krishnamachari, Edmund W Chen
  • Electrostatic discharge protection circuit
    Patent number: 11557896
    Abstract: Provided is an electrostatic discharge protection circuit, including a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor has a first end coupled to a first power rail. The first transistor has a first end coupled to the first power rail, and a control end of the first transistor is coupled to a second end of the first resistor. The second resistor is coupled between a second end of the first transistor and a second power rail. The second transistor has a first end coupled to the first power rail, a control end of the second transistor is coupled to the second end of the first transistor, and a second end of the second transistor is coupled to the second power rail.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: January 17, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Nai Sheng Wu, Chao-Lung Wang, Chia-Lung Lin
  • Power clamp
    Patent number: 11557895
    Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Ken-Hao Fan, Yu-Ti Su, Tzu-Cheng Kao, Ming-Fu Tsai, Chia-Lin Hsu
  • Shallow electrical protection device (GFCI, AFCI, and AFCI/GFCI) system and method
    Patent number: 11557862
    Abstract: An electrical outlet receptacle including a circuit board, a set of fixed contacts and a set of movable contacts, a solenoid, a carriage, a lifting shelf, a slide mechanism, a reset plunger, and an armature.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 17, 2023
    Assignee: Hubbell Incorporated
    Inventors: David Ridgeway, Kenny Padro
  • Spatially variable wafer bias power system
    Patent number: 11551908
    Abstract: A plasma deposition system comprising a wafer platform, a second electrode, a first electrode, a first high voltage pulser, and a second high voltage pulser. In some embodiments, the second electrode may be disposed proximate with the wafer platform. In some embodiments, the second electrode can include a disc shape with a central aperture; a central axis, an aperture diameter, and an outer diameter. In some embodiments, the first electrode may be disposed proximate with the wafer platform and within the central aperture of the second electrode. In some embodiments, the first electrode can include a disc shape, a central axis, and an outer diameter. In some embodiments, the first high voltage pulser can be electrically coupled with the first electrode. In some embodiments, the second high voltage pulser can be electrically coupled with the second electrode.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: January 10, 2023
    Assignee: Eagle Harbor Technologies, Inc.
    Inventors: Timothy Ziemba, Ilia Slobodov, John Carscadden, Kenneth Miller, James Prager
  • Semiconductor device
    Patent number: 11552469
    Abstract: To provide a semiconductor device with a tolerant buffer capable of protecting the internal circuit even when the power supply potential is turned 0 [V]. In the semiconductor device, the protection voltage generating circuit 100 generates the larger of the divided voltage and the power supply voltage Vdd obtained by dividing the voltage padv applied to the pad 4 as the protection voltage protectv. The first protection circuit 200 for protecting the internal logic circuit 2A,2B and the output buffer 10 and the second protection circuit 300 for protecting the input buffer 20 operate protectv this protection voltage.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 10, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Dai Kamimaru
  • Overvoltage protection scheme for connector ports
    Patent number: 11552434
    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for providing overvoltage protection for circuitry coupled to connector ports, such as USB-C ports. One example circuit for overvoltage protection between a connector port and a signal node corresponding to the connector port generally includes a first switch having a first terminal for coupling to the connector port and having a second terminal for coupling to the signal node; a first resistive element coupled in parallel with the first switch; a first transient protection circuit coupled between the signal node and a reference potential node; and a control circuit having an input coupled to the signal node and having a first output coupled to a control input of the first switch.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: January 10, 2023
    Assignee: QUALCOMM Incorporated
    Inventor: Vijayakumar Dhanasekaran