Patents Examined by Do Hyun Yoo
  • Patent number: 7167964
    Abstract: The basic idea comprised of the present invention is to provide two sets of descriptors having each at least three descriptors and each set is used in an alternating manner for defining the location of source and target of the copy operations which are to be performed during the defragmentation procedure. The defragmentation procedure is performed as a sequence of copy operations on copy chunks, i.e., a certain number of sequentially arranged bytes to be copied being part of a valid data block to be copied. In each of said copy operations in said sequence the values which are assigned to said descriptors Change. According to a characterizing feature of the present invention during the whole sequence of copy operations comprised of the defragmentation process one of the two sets of descriptors holds information which is usable for restoring the contents of a copy chunk in case of a power break during a copy operation on said copy chunk. Thus, defragmenting is a safe procedure, and data integrity is assured.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: January 23, 2007
    Assignee: International Business Machines Corporation
    Inventor: Helmut Scherzer
  • Patent number: 6772302
    Abstract: Instant virtual copy operations are adapted for data objects that span storage boundaries such as logical and/or physical DASD subsystems. Initially, a data storage system receives a request to copy a data object contained in the system. The storage system includes multiple storage regions separated by storage boundaries. The regions may correspond to logical or physical DASD subsystems, for example. The storage system determines whether the data object resides in more than one of these regions. If so, the storage system divides the data object into multiple subparts, each subpart contained within a single storage region. Then, the storage system separately performs an instant virtual copy operation for each subpart. On the other hand, if the data object already resides in a single one of the regions, the storage system can perform one instant virtual copy operation for the data object as a whole.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: August 3, 2004
    Assignee: International Business Machines Corporation
    Inventor: John Glenn Thompson
  • Patent number: 6742084
    Abstract: A caching method for selecting variable size data blocks for replacement or removal from a cache includes determining the size and the unreferenced time interval of each block in the cache. The size of a block is the amount of cache space taken up by the block. The unreferenced time interval of a block is the time that has elapsed since the block was last accessed, and may be determined using a least recently used (LRU) algorithm. The recall probability of each block in the cache is then determined. The recall probability of a block is a function of its unreferenced time interval and possibly size and other auxiliary parameters. The caching method then determines a quality factor (q) for each block. The (q) of a block is a function of its recall probability and size. The caching method concludes with removing from the cache the block with the lowest (q).
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: May 25, 2004
    Assignee: Storage Technology Corporation
    Inventors: Richard J. Defouw, Alan Sutton, Ronald W. Korngiebel
  • Patent number: 6728859
    Abstract: An apparatus and method are provided to enable programmable page table accesses in a virtual memory system. The apparatus includes context logic and context configuration logic. The context logic designates an entry within a data structure. The context logic has a plurality of fields, where each of the plurality of fields provides part of a pointer to the entry. The context configuration logic is coupled to the context logic. The context configuration logic prescribes the structure of the each of the plurality of fields. Programming the context configuration logic determines the function by which the context logic derives a useful value from a virtual address associated with an event.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: April 27, 2004
    Assignee: MIPS Technologies, Inc.
    Inventor: Kevin D. Kissell
  • Patent number: 6711649
    Abstract: Load balancing of activities on physical disk storage devices is accomplished by monitoring reading and writing operations to blocks of contiguous storage locations on the physical disk storage devices. A list of exchangeable pairs of blocks is developed based on size and function. Statistics accumulated over an interval are then used to obtain access activity values for each block and each physical disk drive. A statistical analysis leads to a selection of one block pair. After testing to determine any adverse effect of making that change, the exchange is made to more evenly distribute the loading on individual physical disk storage devices.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: March 23, 2004
    Assignee: EMC Corporation
    Inventors: Eitan Bachmat, Yuval Ofek, Avinoam Zakai, Moshe Schreiber, Victoria Dubrovsky, Tao Kai Lam, Ruben Michel
  • Patent number: 6691206
    Abstract: Methods and apparatus are disclosed for interfacing a processor bus or CPU to a computation engine to carry out selected tasks with improved efficiency in the computation engine. The computation engine is controlled by an MCC memory-centric controller that provides microcoded operation of the engine independently of the CPU. Essential interfacing between the processor bus and the computation engine includes storing microcode in a separate memory accessible to the MCC controller, or downloading microcode from the CPU/processor bus as needed for a specific task. The MCC controller can reconfigure the computation engine, such as memory block allocation, word size, etc. under microcode control, so that new or user-proprietary algorithms such as those used in dsp can be implemented using a standard computation engine without redesign. Execution of selected tasks on the computation engine is triggered automatically by decoding instructions that appear on the processor bus.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: February 10, 2004
    Assignee: Marger Johnson & McCollom, P.C.
    Inventor: Richard Rubinstein
  • Patent number: 6671792
    Abstract: A directory tag for each cache line in a memory within a multiprocessor distributed memory system includes a share mask and an alias signature. The share mask is used to keep track of entities of the system that share the cache line, and is encoded into a fixed length field having a number of bits that is significantly less than the number of the entities. The share mask is utilized for maintaining coherency among shared data in the system. Before a request to access a location of a memory is granted, the share mask is used to identify each entity or a group of entities that share the particular location, and an invalidate message is sent to each of the identified entity or group of entities, eliminating the need to broadcast the message to all entities in the system, and thus conserving the communication bandwidth of the system.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: December 30, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Curtis R. McAllister
  • Patent number: 6636934
    Abstract: A data storage system having a plurality of disk drives. Each one has a pair of bi-directional ports. A pair of directors controls the flow of data to and from the disk drives. A first fiber channel port by-pass selector section is provided. The first fiber channel by-pass selector section includes: an input/output port coupled to a first one of the directors; and, a plurality of output/input ports connected between a first one of the ports of the plurality of disk drives through a first plurality of fiber channel links. The first fiber channel port by-pass selector section is adapted to couple the first one of the directors serially to one, or ones, of the first ports of the plurality of disk drives through a first fiber channel selectively in accordance with a control signal fed to the first fiber channel by-pass selector section. The first fiber channel includes one, or more, of the first plurality of fiber channel links.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: October 21, 2003
    Assignee: EMC Corporation
    Inventors: Thomas Earl Linnell, William R. Tuccio, Christopher J. Mulvey
  • Patent number: 6636938
    Abstract: A sound generator, capable of improving a DRAM download speed and reducing power consumption when operating a DRAM download by applying a dedicated download logic, may increase the download speed up to 8 times at the minimum to 62 times at the maximum, and reduce power consumption by decreasing unnecessary clockings. In addition, since the sound generator according to the present invention does not access a parameter memory when downloading, previously processed data is not erroneously handled, and there is no need to rewrite new data to an internal memory after the download operation is completed.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: October 21, 2003
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Yeon Ok Kim
  • Patent number: 6629214
    Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: September 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, John Steven Dodson, Guy Lynn Guthrie, William John Starke
  • Patent number: 6625703
    Abstract: Verification of a primary or backup copy of vital information of a processing system employs a pseudo-fixed reference identifier, defined as an identifier unlikely to change over the life of the system, and controls which copy of vital information is correct. The primary copy of vital information is associated with a copy of the pseudo-fixed reference identifier and a backup copy of the vital information is associated with a copy of the pseudo-fixed reference identifier. A processor, when triggered, reads the pseudo-fixed reference identifier, compares it to the stored copies of the identifier of the primary and backup non-volatile storage. (1) If the read pseudo-fixed reference identifier matches the primary copy of the identifier, the processor indicates the vital information is valid. (2) If the read pseudo-fixed reference identifier matches the backup only, indicating that the backup copy of vital information is to be restore copied to become the primary copy.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Brian Gerald Goodman, Ronald Faye Hill, Jr., Leonard George Jesionowski, Timothy Keith Pierce, Robin Daniel Roberts
  • Patent number: 6625701
    Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, John Steven Dodson, Guy Lynn Guthrie, William John Starke
  • Patent number: 6625686
    Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: September 23, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems, Co., Ltd.
    Inventors: Masami Hasegawa, Yoichi Satoh, Yuuji Yanagisawa, Yoshio Iioka, Yoshimi Kitagawa, Makio Uchida
  • Patent number: 6622197
    Abstract: A dynamic random access memory device includes a mode register set, a refresh period selector, and a bit organization selector. The mode register set outputs decoded signals having values according to a user-stored value in the mode register set. The mode register set can be accessed in response to an address externally supplied when a mode set command is applied. The refresh period selector generates a plurality of refresh period select signals in response to the decoded signals. A refresh counter in the device generates a sequence of row addresses having a timing according to a refresh period determined from an activated refresh period select signal. The bit organization select circuit generates a plurality of bit organization select signals in response to the decoded signals from the mode register set. A data output multiplexer in the device selects some of the read data bits according to a bit organization determined by one of the bit organization select signals.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: September 16, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hoon Kim
  • Patent number: 6622217
    Abstract: The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: September 16, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Mosur K. Ravishankar, Robert J Stets, Jr., Andreas Nowatzyk
  • Patent number: 6622202
    Abstract: A method of operating a RAM memory having a plurality of memory addresses for storing data, the method being performed with a timing based on clock signals spaced by clock periods and comprising the steps of: receiving an address and a function signal specifying a function to be performed on data associated with that address; determining whether the same address has been received during a predefined number of preceding clock periods; generating a first data item representing data associated with the received address; modifying the first item according to the function signal to generate a second data item associated with the address, and writing the second data item to the address in the RAM and retaining a separate record of the last n second data items, the step of generating a first data item being performed by: (i) if the result of the determination is negative, generating the first data item to be equal to data stored by the RAM in the address, and (ii) if the result of the determination is positive, gene
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: September 16, 2003
    Assignee: Xyratex Technology Limited
    Inventors: Steven Raymond Carroll, Ian David Johnson
  • Patent number: 6622204
    Abstract: An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: September 16, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Christopher W. Jones, Steven J. E. Wilton
  • Patent number: 6618796
    Abstract: There is provided a data storage device which reads data from and/or writes data to a memory medium, comprising: an acquisition unit for acquiring management information which is recorded by a predetermined form in said memory; and a controller for converting the management information into another form. The controller rearranges the management information to convert the management information into another form, and also the controller restores the converted management information to the predetermined form according to a relationship between a first identifier recorded on the memory medium and a second identifier recorded in the data storage device. When, for example, the two identifiers match, the acquisition unit can acquire the management information, and the reading and writing of data is enabled.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: September 9, 2003
    Assignee: Fujitsu Limited
    Inventors: Teruji Yamakawa, Kiyomi Imamura
  • Patent number: 6615335
    Abstract: Disclosed is a method of compressing information for storage in a fixed size memory. The data items (D(k)) that constitute the information are divided into pieces (D(s,k)) of decreasing significance. For example, the DCT blocks of an image are hierarchically quantized (3). The memory (5) is organized in corresponding memory layers (501-504). Successive memory layers have a decreasing number of memory locations. Every time a data item is applied to the memory, its less significant data pieces will have to compete with corresponding data pieces of previously stored data items. Depending on its contribution to perceptual image quality, the applied data piece is stored or the stored data piece is kept. Links (511-513, 521-522) are stored in the memory to identify the path along which a data item is stored. Eventually, the image is automatically compressed so as to exactly fit in the memory. FIG. 2.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: September 2, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Richard Petrus Kleihorst, Renatus Josephus Van Der Vleuten, Andre Krijn Nieuwland
  • Patent number: 6615308
    Abstract: In one embodiment, monitoring data traffic through a memory controller; and dynamically and automatically selecting a burst length for data transactions through a memory controller in response to the monitored data traffic.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: September 2, 2003
    Assignee: Intel Corporation
    Inventor: Blaise B. Fanning