Abstract: Chip cards comprising a microprocessor and a memory are used for various applications. It is also desirable that such chip cards can be used for different applications. This requires a strict and reliable separation of the various user programs so that mutual accessing is not possible. This is achieved notably by subdivision into a system mode, in which all access rights are free, and a user mode which is adjusted by way of a given bit in the program status word. This mode bit controls inter alia a separation in the bus for the special function registers so that given registers are not accessible in the user mode. These registers may contain information enabling the access to given memory sections only, so that this access cannot be modified in the user mode.

Abstract: A method and apparatus for handling an accessed bit in a page table entry is provided. When a page table entry is not present in a translation lookaside buffer (TLB), an electrical circuit causes a TLB miss exception and branching to a first software exception handler. The first software exception handler fetches the page table entry from main memory. The first software exception handler places the page table entry in the TLB. An electrical circuit determines whether an accessed bit of the page table entry has not been asserted. If the accessed bit is not asserted, an electrical circuit causes an accessed bit exception and branches execution to a second software exception handler. The second software exception handler asserts the accessed bit in the page table entry in main memory. The second software exception handler returns control back to the original memory access, causing execution to resume where it had left off prior to the TLB miss exception.

Abstract: An improved mechanism for managing an object cache is disclosed. An object cache manager receives a request for an object resident in an object cache. A determination is made as to whether the requested object is currently within a particular portion of the object cache. If the requested object is within this particular portion, then the object cache manager keeps the requested object within this portion of the cache by maintaining the requested object at its current position relative to other objects in the object cache. By removing the overhead of repositioning objects within a particular portion of the object cache, the efficiency of object cache management is significantly improved.

Abstract: A method and apparatus for determining the address of a highest priority matching entry in a segmented content addressable memory device. For one embodiment, a segmented CAM device is disclosed that includes m CAM array blocks each having n rows of CAM cells coupled to one of n corresponding match lines. The CAM array blocks have a predetermined priority based on their addresses such that the first CAM array block has the highest priority addresses and the mth CAM array block has the lowest priority addresses. Comparand data is provided for comparison with entries in each of the CAM array blocks. Each row of CAM cells in each block has a row enable logic circuit. A main priority encoder is coupled to the row enable logic circuits of the mth CAM array block. Each CAM array block also has an associated match flag circuit to determine a match flag signal for the block. A block priority encoder encodes the match flag signals into a block address of the highest priority matching location.

Abstract: A data processing network including a local system and a geographically remote system. Each of the local and remote systems includes a data storage facility. The remote data storage facility mirrors the local data storage facility. In a normal operating mode, the local and remote systems operate in near synchronism or in synchronism. In an alternate operating mode, writing operations at the local system immediately update the storage devices in the local data storage facility. Transfers of corresponding data to the remote data storage facility are made independently of and asynchronously with respect to the operation of the local system.

Abstract: A tag-based write-combining apparatus in a microprocessor. The apparatus includes a register that stores the store address of the last write-combinable store passing through the store stage of the pipeline. Tag allocation logic compares the last store address with the store address of a new store and allocates the same tag as was previously allocated to the last store if the addresses are in the same cache line, and assigns the next incremental tag otherwise. Tag registers store write buffer tags associated with store data in write buffers waiting to be written to memory on the processor bus. When the new store reaches the write buffer stage, tag comparators compare the new store tag with the write buffer store tags. If the tags match, the write buffer control logic combines the new store data with the store data in the write buffer with the matching tag.

Abstract: Provided is a method, system, and program for releasing storage space in a first and second storage devices. Updates to the first storage device are copied to the second storage device to provide secondary storage for the updates. A first and second tables map data sets to addresses in the first and second storage devices, respectively. A first command is detected to invalidate data sets in the first table. The addresses in the first table comprise virtual addresses, and a third table provides a mapping of the virtual addresses to physical storage locations in the first storage device. A second command is generated to update the second table to invalidate the data sets in the second storage device invalidated in the first table by the first command. A third command is detected to invalidate the virtual addresses in the third table used by the data sets invalidated in the first table to free the physical storage locations in the first storage device pointed to by the invalidated virtual addresses.

Abstract: A multipurpose memory device suitable for a broader range of applications, whether requiring the reading of data in an asynchronous mode with random access (as in a standard memory) or in a synchronous sequential mode with sequential or burst type access, is capable of recognizing the mode of access and the mode of reading that is currently required by the microprocessor. The memory device self-conditions its internal circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation.

Abstract: A Time Division Multiple Access (TDMA) mobile station architecture consuming less power and random access memory (RAM) is presented herein. The mobile station includes a coprocessor which executes frame programs. The frame programs include instructions which address memory. The memory includes page addresses and byte addresses. The instructions of the frame program address the page addresses and byte addresses. A particular page address is reserved as a null page address, wherein any instruction addressing the null page address causes the memory locations of the most recently accessed memory page to be accessed.

Abstract: A flash memory rewriting circuit capable of rewriting a flash ROM without Presenting any problem from the viewpoint of security of programs. In a transfer Program storing region of the flash ROM is stored a program to activate a CPU of a microcontroller and to transfer a rewriting data from external devices to peripherals. On a mask ROM is written, in a fixed manner, a program to activate a CPU and to write the rewriting data on a region other than the flash ROM. Because the program stored in the transfer program storing region is installed by users, no on except user can read or rewrite the program.

Abstract: Load balancing of activities on physical disk storage devices is accomplished by monitoring reading and writing operations to blocks of contiguous storage locations on the physical disk storage devices. A list of exchangeable pairs of blocks is developed based on size and function. Statistics accumulated over an interval are then used to obtain access activity values for each block and each physical disk drive. These activities are represented as disk seek, latency and data transfer times. A statistical analysis leads to a selection of one block pair. After testing to determine any adverse effect of making that change, the exchange is made to more evenly distribute the loading on individual physical disk storage devices.

Abstract: The invention provides a method for removing code (applications and data) from read-only memory, and compacting the remaining code in memory either as an application is deleted or when there is not sufficient room to hold a new application. One or more “spare” memory segments are reserved for use during compaction. Where the code for removal shares a memory segment with other code that is not to be removed, the other code is copied to a spare memory segment, and then swapped back to its original location. The code can then be compacted to remove the “holes” left by the erased code.

Abstract: A data storage system wherein a host computer is in communication with a bank of disk drives through an interface. The interface includes: a memory; a plurality of directors for controlling data transfer between the host computer and the bank of disk drives as such data passes through the memory; and a plurality of busses in communication with the directors and the memory. Each one of the directors includes a central processing unit. The central processing unit includes: (A) a microprocessor; (B) a main memory; and (C) a microprocessor interface.

Abstract: The present invention relates to using memory in a computer. In particular, the present invention relates to allocating a portion of computer-system memory as a cache, making the allocated portion accessible to device drivers and hiding the allocated memory portion from the operating system. In one embodiment of the present invention, an amount of system memory is allocated for use as a direct memory access (“DMA”) buffer. The allocated memory is mapped as write combining, and this write combining memory is made available to a device driver.

Abstract: A cache memory control device enables an external instruction ROM to be co-owned by plural processors while minimizing the lowering of the processing performance of the processor and curtailing the number of external terminals of the LSIs. In a multi-processor system having a processor, an instruction RAM bank and an instruction RAM controller for each physical layer PHY, there is provided one instruction ROM for storing instruction data. The RAM controller of each PHY outputs time allowance information to a pre-fetch request of the instruction data. If there are simultaneously output pre-fetch requests from plural PHYs, the pre-fetch controller selects a pre-fetch request having the smallest time allowance.

Abstract: In a method of processing a bus transaction, an address is retrieved from the bus transaction and referred to a queue of pending transaction. A match indicator signal is returned from the queue. If the match indicator signal indicates a match, a snoop probe for the bus transaction is blocked.

Abstract: The invention is aimed at providing a high-speed processor system capable of performing distributed concurrent processing without requiring modification of conventional programming styles utilizing a high speed process or system and cache memories with processing capabilities. The processor system in accordance with the invention has a CPU, a plurality of parallel DRAMs, and a plurality of cache memories arranged in a hierarchical configuration. Each of the cache memories is provided with an MPU which is binarily-compatible with the CPU and which has a function to serve as a processor with, amongst other features, both a cache logic function and a processor-function.

Abstract: A method, system and program for controlling access to computer memory are provided. The present invention comprises receiving a work request from a user, wherein the work request comprises an index portion and a protection portion. The index portion of the work request is used to locate an element in an address translation and protection table. The protection portion of the work request is then compared with a protection key in the table element, and access to memory is granted only if the protection portion and protection key match.

Abstract: A memory system and method of using same are provided. In one embodiment of the present invention, a novel memory operation protocol may be used to facilitate the execution of memory operations in the memory system. These memory operations may include atomic read-modify-write operations that may involve arithmetic and/or logical operations of greater complexity than those that may be carried out in the prior art.

Abstract: Data is written into a circular buffer at an address pointed to by a write pointer. A number is written into the address with the data. Each time the circular buffer is traversed by the write pointer this number increments modulo a predetermined number. This number makes the circular buffer appear longer than it really is and can be used to identify underruns. The buffer has application in a segmentation and reassembly device for ATM constant bit rate services.