Patents Examined by Do Hyun Yoo
  • Patent number: 6615335
    Abstract: Disclosed is a method of compressing information for storage in a fixed size memory. The data items (D(k)) that constitute the information are divided into pieces (D(s,k)) of decreasing significance. For example, the DCT blocks of an image are hierarchically quantized (3). The memory (5) is organized in corresponding memory layers (501-504). Successive memory layers have a decreasing number of memory locations. Every time a data item is applied to the memory, its less significant data pieces will have to compete with corresponding data pieces of previously stored data items. Depending on its contribution to perceptual image quality, the applied data piece is stored or the stored data piece is kept. Links (511-513, 521-522) are stored in the memory to identify the path along which a data item is stored. Eventually, the image is automatically compressed so as to exactly fit in the memory. FIG. 2.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: September 2, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Richard Petrus Kleihorst, Renatus Josephus Van Der Vleuten, Andre Krijn Nieuwland
  • Patent number: 6615313
    Abstract: An input/output control device uses all of its cache memory effectively and allows cache memory modules to be added in increments of one. When cache memory included in the input/output control device is operating normally and the input/output control device receives a write request from a processing device, the input/output control device returns a write request completed response after writing data to cache memory as set forth in configuration information included in the input/output control device. The write data in the cache memory is then written to one or more disk devices asynchronously with the write completed response. When there is a problem with a cache memory module, the write data that was to be written to the region controlled by the cache memory module where the problem occurred is divided among the remaining cache memory modules.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: September 2, 2003
    Assignee: Fujitsu Limited
    Inventors: Tadaomi Kato, Hideaki Omura, Hiromi Kubota
  • Patent number: 6606697
    Abstract: A page table on a main storage contains a correspondence between guest virtual address and a host real address, and a TLB in a processor holds said correspondence calculated by a previous address translation. A PTBR holds a real address of a page table. When a processor detects a TLB purge, the processor starts a host when detecting a TLB purge. The host examines a virtual space change processing executed by the guest, and stores a correspondence between a new guest virtual address and a new host real address in the page table.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: August 12, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kuniaki Kawahara, Yukihiro Seki, Takashi Shimojo
  • Patent number: 6606690
    Abstract: A method, system, and apparatus for accessing a plurality of storage devices in a storage area network (SAN) as network attached storage (NAS) in a data communication network is described. A SAN server includes a first interface and a second interface. The first interface is configured to be coupled to the SAN. The second interface is coupled to a first data communication network. A NAS server includes a third interface and a fourth interface. The third interface is configured to be coupled to a second data communication network. The fourth interface is coupled to the first data communication network. The SAN server allocates a first portion of the plurality of storage devices in the SAN to be accessible through the second interface to at least one first host coupled to the first data communication network. The SAN server allocates a second portion of the plurality of storage devices in the SAN to the NAS server.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: August 12, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Michael Padovano
  • Patent number: 6606689
    Abstract: A video game system includes an audio digital signal processor, a main memory and an audio memory separate from the main memory and storing audio-related data for processing by the audio digital signal processor. Memory access circuitry reads non-audio-related data stored on a mass storage device and writes the non-audio-related data to the audio memory. The non-audio-related data is later read from the audio memory and written to the main memory.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: August 12, 2003
    Assignee: Nintendo Co., Ltd.
    Inventors: Howard H. Cheng, Dan Shimizu, Genyo Takeda
  • Patent number: 6606695
    Abstract: The storage regions under command of a storage controller can be simply enabled and disabled to access to by automatically registering connected host computers. Such system can be achieved by taking a step of acquiring N_Port_Name information included in a login frame from the host computers, and a step of displaying a table of access right of host computers to a logical unit under command of storage controller. A security table for the storage controller can be generated by supervisor's setting the access enable/disable flag information.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: August 12, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshimitsu Kamano, Kenichi Takamoto
  • Patent number: 6606688
    Abstract: A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: August 12, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masaru Koyanagi, Disuke Yamane, Hideya Akashi, Yuji Tsushima, Tadayuki Sakakibara
  • Patent number: 6604178
    Abstract: A method and apparatus for calculating an expected access time associated with one of a plurality of disk drive commands employs one or more neural networks. A plurality of disk drive commands received from an external source are stored in a memory, typically in a queue. Using a neural network, an expected access time associated with each of the queued commands is determined. Determining the expected access time associated with each of the queued commands involves determining a time for performing a seek and settle operation for each of the queued commands and a latency time associated with each of the queued commands. The command indicated by the neural network as having a minimum expected access time relative to access times associated with other ones of the queued commands is identified for execution.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: August 5, 2003
    Assignee: International Business Machines Corporation
    Inventor: David Robison Hall
  • Patent number: 6604175
    Abstract: A memory system comprises a memory, a memory controller and a cache. The memory stores a plurality of data packets, which are associated with a plurality of data types. The memory controller receives requests for data packets from a processing unit and passes requested data packets from the memory to the processing unit. The cache comprises a plurality of independently cached areas. The memory controller passes requested data packets from the memory to the cache. The memory controller passes requested data packets from the cache to the processing unit in response to subsequent data packet requests from the processing unit to the memory controller. The memory controller assigns each independently cached area in the cache to store data packets associated with one item type where an item type may be a texture, thread, task or process. Each independently cached area is associated with a data usage indicator.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: August 5, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Thomas Patrick Dawson
  • Patent number: 6601135
    Abstract: A no-integrity management method and system for managing logical volumes of a computer system. The no-integrity refers to the fact that the availability status of each partition within the mirrored logical volumes is not written to a direct access storage device but instead stored within a volatile memory. When the computer system is shutdown the availability status information is discarded, and the availability status of each partition is marked as active upon first open of a partition after startup of the computer system.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Gerald F. McBrearty, Ram Pandirl, Johnny M. Shieh
  • Patent number: 6601158
    Abstract: According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of the second counter. The apparatus also includes a lookup table addressed by the current count value of the first counter, as well as a combining circuit coupled to the output of the lookup table and to receive the current count value of the second counter.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: July 29, 2003
    Assignee: PMC-Sierra, Inc.
    Inventors: Curtis Abbott, Homayoun Shahri
  • Patent number: 6601148
    Abstract: A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A set of Work Requests is then placed on the work queue, behind the first Bind WQE wherein the work requests invoke operations that access the first Memory Window. A second Bind WQE is then placed on the work queue, behind the first set of Work Requests. This second Bind WQE defines parameters associated with a second Memory Window. A second set of Work Requests is placed on the work queue behind the second Bind WQE and invoke operations that access the second memory window. The Memory Windows can be associated with a common Memory Region and have different addresses and lengths or different access rights. In another embodiment, the first and second Memory Windows can be associated with different Memory Regions.
    Type: Grant
    Filed: March 1, 2001
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Renato John Recio, Steven L. Rogers, Bruce Marshall Walk
  • Patent number: 6601145
    Abstract: A multiprocessor computer system in which snoop operations of the caches are synchronized to allow the issuance of a cache operation during a cycle which is selected based on the particular manner in which the caches have been synchronized. Each cache controller is aware of when these synchronized snoop tenures occur, and can target these cycles for certain types of requests that are sensitive to snooper retries, such as kill-type operations. The synchronization may set up a priority scheme for systems with multiple interconnect buses, or may synchronize the refresh cycles of the DRAM memory of the snooper's directory. In another aspect of the invention, windows are created during which a directory will not receive write operations (i.e., the directory is reserved for only read-type operations). The invention may be implemented in a cache hierarchy which provides memory arranged in banks, the banks being similarly synchronized.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, James Stephen Fields, Jr., Sanjeev Ghai, Guy Lynn Guthrie, Jody B. Joyner
  • Patent number: 6601157
    Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: July 29, 2003
    Assignee: Broadcom Corporation
    Inventors: Mark Taunton, Sophie Wilson, Timothy Martin Dobson
  • Patent number: 6601133
    Abstract: A method balances workloads of storage devices of a storage subsystem. The method includes reading a mailbox to obtain control parameters and collecting historical data on numbers of accesses to storage volumes of the storage devices. The control parameters are written in the mailbox by host devices. The method also includes selecting data swaps that lead to better balanced workloads for storage devices based on the historical data. The act of selecting and/or the act of collecting being initialized by the control parameters.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: July 29, 2003
    Assignee: EMC Corporation
    Inventors: Avinoam Zakai, David Wayne DesRoches, Victoria Dubrovsky, Shai Bar-Nefy, Ruben Michel
  • Patent number: 6601142
    Abstract: A method for enhanced fragment caching. The method can include identifying in at least one of first and second retrieved page fragments a variable object utilized by the fragment upon execution to produce dynamic content. Separate cache entries can be written for the first and second retrieved page fragments where the first and second retrieved page fragments differ in ways other than an evaluation of the variable object. Otherwise, a single cache entry can be written for both the first and second retrieved page fragments where the first and second retrieved page fragments differ only in the evaluation of the variable object.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: John S. Cox, Brian Keith Martin, Daniel Christopher Shupp
  • Patent number: 6601136
    Abstract: A media server system and process are disclosed that have device independent near-online storage support. A plurality of media assets are stored in online storage, and a plurality of media assets are stored on tertiary storage devices in tertiary storage to provide near-online storage. A media server, having access to the online storage and the tertiary storage, receives a user request for a media asset. The media server then determines whether the requested media asset needs to be loaded from the tertiary storage. If so, the media server allocates space in the online storage for the requested media asset. A transfer process specific to the tertiary storage devices is then used to transfer content of the requested media asset to the online storage.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: July 29, 2003
    Assignee: Kasenna, Inc.
    Inventors: Lakshminarayanan Gunaseelan, Eliahu Lauris
  • Patent number: 6598125
    Abstract: A method of caching information between work sessions for future use is described. The method efficiently determines those blocks of information least likely to be required for future use and preferentially discards such blocks from the cache when additional cache storage space is needed. The method also provides for the dynamic allocation of cache space between work sessions of different content.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: July 22, 2003
    Assignee: Exent Technologies, Ltd
    Inventor: Amnon Romm
  • Patent number: 6594723
    Abstract: A computer system includes a Flash or other nonvolatile memory. A program(s) to coordinate data transfers is loaded into a volatile system memory to transfer data from an external device to the Flash memory. The data transferred from the external device to the Flash memory can be transferred to a previously unused portion of the Flash memory, or alternatively can overwrite a previously used portion of the Flash memory. According to one aspect of the invention, the data is transferred from the external device to the volatile system memory and then from the volatile system memory to the Flash memory, allowing additional verification steps to help insure that the data is transferred intact. According to another aspect of the invention, data is copied from the external device to the Flash memory on a portion by portion basis, leaving a set of critical portions to be transferred last.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: July 15, 2003
    Assignee: Microsoft Corporation
    Inventors: Craig Chapman, Hang Li, Mark M. Moeller
  • Patent number: 6594743
    Abstract: A disk-cloning method and system is provided for cloning computer data from a source disk to a target disk. This disk-cloning method and system can be utilized, for example, in the computer assembly line to clone a preselected set of software programs to the main hard disk of each computer unit, or as a backup to a hard disk. This disk-cloning method and system is characterized in that the source data are read from the source disk and written onto the target disk in a sector-by-sector manner rather than in a file-by-file manner as the prior art. This feature allows the cloning procedure to be more efficiently carried out than the prior art. Moreover, it allows the disk-cloning procedure to be performed without having to make modifications to the existing FDT (File Directory Table) and FAT (File Allocation Table) on the target disk, thus ensuring the system security of the target disk. This disk-cloning method and system is therefore more reliable and efficient to use than the prior art.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: July 15, 2003
    Assignee: Inventec Corporation
    Inventors: Tong S. Chen, Kuang Shin Lin, Yong Jun Shi