Abstract: A method of monitoring the integrity of the path and flow of digital PCM data from a source end to a receiving end which includes generating a pseudo-random sequence of bits at the source end, transmitting the pseudo-random sequence of bits together with the PCM data through a transmission path to a receiving end, and applying the pseudo-random sequence of bits to a pseudo-random bit sequence checker at the receiving end.

Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.

Abstract: A data receiving system, for equalizing a reception signal by using a decision feedback equalizer when the reception signal is formatted to have a sync signal positioned at the center of a burst, comprises a receiving buffer for storing reception data, training calculation means for obtaining a tap coefficient by performing a training using the sync signal involved in the reception data, a direction selecting means for selecting a preferable direction for a tracking of the decision feedback equalizer, based on a judgement as to which direction is preferable for the decision feedback equalizer between the direction identical with the receiving sequence of the reception data and the direction opposed to the receiving sequence of the reception data, and a tracking calculation means for performing the calculation of the decision feedback equalizer by tracking the reception data along the preferable direction using the tap coefficient given from the training calculation means having executed the training along the

Abstract: A quadrature sampling system and method (BQS) and a hybrid quadrature sampling and channel equalization system and method (BQS/EQ) which convert input signals to baseband inphase and quadrature signal components. The BQS system includes an inphase signal channel including a first set of K filters, and a signal summer which sums the outputs of the first set of K filters to produce the inphase signal component; a quadrature signal channel including a second set of K filters, and a signal summer which sums the outputs of the second set of K filters to produce the quadrature signal component; and a controlled switch which provides input samples to the inphase and quadrature signal channels so that each filter of both channels receives one input sample of each sequence. The BQS/EQ system includes first and second sets of signal processing filter pairs, each pair including an inphase and a quadrature filter.

Abstract: A technique for modulating and demodulating CPM spread spectrum signals and variations of CPM spread spectrum signals. A transmitter divides a signal data stream into a plurality of data streams (such as I and Q data streams), independently modulates the I and Q data streams using CPM or a related technique, and superposes the plurality of resultants for transmission. A receiver receives the superposed spread spectrum signal and simultaneously attempts to correlate for a plurality of chip sequences (such as I and Q chip sequences), and interleaves the correlated I and Q data streams into a unified signal data stream. In one embodiment, the receiver separates the received spread spectrum signal into real and imaginary parts, attempts to correlate both real and imaginary parts for a plurality of chip sequences, and combines the real I, real Q, imaginary I, and imaginary Q signals into a unified signal data stream.

Abstract: Method and apparatus for reducing the contributions of ionospheric propagation time delay error, multipath signal error and receiver noise error from signals received in a Satellite Positioning System (SATPS) from one or more SATPS satellites by formation and appropriate filtering of differences of signals DD that are differences of SATPS signals received by the SATPS receiver/processor. A difference signal DD of code-phase-derived, ionosphere-free signals and carrier-phase-derived, ionosphere-free signals is formed, and this difference signal is passed through a first statistical processing filter with an associated time constant .tau.1 in the approximate range 50-500 sec, to produce smoothed or filtered first difference signal with the estimated receiver noise error reduced or removed. The difference signal DD is passed through second and third statistical processing filters having associated time constants .tau.2=5-20 sec and .tau.

Abstract: A jitter suppression circuit for a synchronous transmission network has a write clock generator for carrying out positive or negative stuffing, a buffer memory for storing data related to the main signals, a byte-bit converter, a clock mask, an N-phase clock generator, a read clock generator, and a smoothing unit. The byte-bit converter has an accumulator for accumulating bits related to the positive or negative stuffing according to the byte stuffing signal and a distributor for distributing the accumulated bits according to a moving average for a predetermined period, to generate smoothed bit stuffing signals. The clock mask masks clock signals corresponding to overhead bytes among the received clock signals. The N-phase clock generator divides the period of the output clock signal of the clock mask by N, to generate N-phase clock signals. The read clock generator sequentially selects the N-phase clock signals according to the bit stuffing signals, to generate clock signals for reading the buffer memory.

Abstract: A data detector is disclosed which includes a source of a data signal representing a sequence of symbols. A maximum likelihood sequence detector, is coupled to the data signal source, and produces a most likely survivor sequence, which includes a plurality of symbols. A decision feedback equalizer and a phase detector, controlling the timing of the sampling of the data signal, are made responsive to the most likely survivor sequence.

Abstract: In digital communications over a limited-bandwidth channel such as a radio-broadcast channel, multiple phase-amplitude shift keyed (MPASK) modulation is preferred using close packed hexagonal code. In quantizing such signals, a representation of an equalized received signal is transformed such that, to each symbol of the constellation, there corresponds a respective point on a square grid. A symbol of the constellation is determined as a quantized representative of the received signal by its selection as the one or the other of two symbols of the constellation having transformed representations at vertices of the square or rectangle in which the transformed signal lies. Such quantizing can be performed at a rate which is independent of the size of the constellation, and can be combined with similarly advantageous decoding in a receiver.

Abstract: A data discriminating circuit is provided on the receiver side of a digital signal transmission system, and performs data discrimination with a proper phase relation settled between data and a clock signal. In the discrimination circuit, a data discriminating section discriminates input data in synchronism with a clock signal and outputs resultant data as discriminated data, a phase-relation judging section judges a phase relation between the input data and the discriminated data, a clock phase controller produces a phase control signal to control and initially-determined phase of the clock signal, based on an output of the phase-relation judging section, and a clock phase judging section determines a phase of the clock signal and alters the initially-determined phase of the clock signal in accordance with the phase control signal from the clock phase controller.

Abstract: A cable loss simulator for a serial digital signal source adapts a constant resistance, bridged-T passive network to simulate the frequency-loss characteristics of a reference coaxial cable. The cable loss simulator is selectively coupled into the output path of the serial digital signal source to simulate the serial digital signal after transmission through the reference coaxial cable. The cable loss simulator has a resistive input section for impedance matching with the serial digital signal source and a bridged-T section with multiple breakpoints to simulate the frequency-loss characteristic of the reference coaxial cable.

Abstract: A demodulation correcting circuit for an FSK signal receiver which include an AFC for correcting a reception frequency error to provide stabilized demodulation, said demodulation correcting circuit comprising subtracting circuit followed to a loop filter for eliminating or correcting a variation of the center frequency of the FSK modulation signal, which is caused by the fact that the AFC responds to low frequency components including DC of the FSK modulation signal and which brings about a decrease of noise margin.

Abstract: An OCDMA spread spectrum communication system is provided with a PN encoded acquisition channel signal which is free of Radamacher functions. This provides a technique for very rapid acquisition of the PN code and data symbol timing; enables accurate PN chip time tracking with a minimum of power; enables accurate frequency tracking with a minimum of power; provides a technique for accurate signal power measurement at the receiver; enables the receiver to maintain code lock during deep fades; and penetrates into areas of high attenuation for paging or to alert user that he has a call waiting.

Abstract: Serial high speed interconnect devices are integrated with semiconductor devices for simple and reliable communications and control between a plurality of semiconductor devices. The serial high speed interconnect devices transfer the data serially at a rate fast enough to replace large parallel data and address buses that require one conductive path per bit of data. Eliminating large parallel data and address buses allows the integrated circuit containing the semiconductor device to be smaller, simpler and lower in cost. The subsequent reduction in the size of the integrated circuits improves the layout density of electronic systems and reduces crosstalk and other undesirable signal transfer anomalies. The serial high speed interconnection devices are implemented with a low cost serial interface circuit technology that may be easily implemented on a semiconductor die in conjunction with the main circuits.

Abstract: In a noise shaper comprising first and second cascaded integrators, a quantizer receiving an output signal of the second integrator, and a feedback path for feeding back an output of the quantizer to each of the first and second integrators, the first integrator includes an adder having a first input receiving art input signal applied to the first integrator, a delay circuit receiving an output of the adder to output a one-sample-delayed signal, and a multiplying circuit having an input connected to an output of the delay circuit for multiplying the one-sample-delayed signal outputted from the delay circuit, by a positive coefficient "0.999". An output of the multiplying circuit is connected to a second input of the adder. An output of the delay circuit constitutes the output of the first integrator.

Abstract: In an automatic frequency control device for tuning the frequency of an intermediate frequency (IF) signal to a desired or target frequency, a frequency mixer subtracts the frequency of a received signal coming in through an antenna from the frequency of a local oscillation signal output from a voltage controlled oscillator. A reference oscillator outputs a reference oscillation signal on the basis of a control voltage from a digital/analog converter. The local oscillation signal from the voltage controlled oscillator is synchronous in phase to the reference oscillation signal. A frequency measurement circuit measures the frequency of the IF signal. A subtracter subtracts the frequency of the IF signal from the target frequency and thereby produces a frequency error.

Abstract: A method and apparatus of determining signal strength, regardless of the signal data rate, in a receiver receiving signals from a variable rate transmitter. The incoming signal is comprised of a series of frames. Each frame is comprised of a number of power control groups containing data. The number of the power control groups containing data within each frame is dependent on the unknown data rate. The position of the power control groups within the frame is a pseudorandom. The signal strength of an incoming signal of unknown data rate is determined based upon an active set of power control groups within a frame. The active set of power control groups contain data independent of the unknown data rate. This signal strength information may be used to indicate that the signal strength is sufficient to perform further signal processing.

Abstract: The number of oscillators required to construct a digital radiocommunication terminal can be reduced and a circuit used for the digital radiocommunication terminal can be reduced in size. For this purpose, the digital radiocommunication terminal for effecting information transmission using an N (integer)-phase-shift-keyed signal (identification symbol number N=4 upon .pi./4 shifted QPSK modulation), is constructed such that an oscillation frequency generated from a reference oscillator employed with a frequency synthesizer is selected to have a common multiple of a second intermediate frequency and an identification symbol phase N and is supplied to a detector for outputting received data therefrom.

Abstract: A novel code division multiple access (CDMA) system and apparatus is provided which permits a plurality of encoded modulated data messages to be transmitted simultaneously on the same channel in one frequency band as a composite CDMA signal. An identification signal is generated and spread by a spreading signal having a duty cycle less than fifty percent to produce a combined signal which is transmitted to a receiver having a tapped delay with a plurality of taps each of which produce a replica of the received combined signal delayed by an odd multiple of the duty cycle of the spreading signal. Each of the replica signals is multiplied by a predetermined weighted value to produce weighted delayed signals and a controller responsive to the received combined signal, is employed for controlling individual weighted delayed signals which are then combined to suppress the spreading signal leaving the identification signal.

Abstract: A coherent detection method including a step of estimating a transfer function of a propagation path using pseudo-pilot signals which consist of some information symbols adjacent to pilot signals. The information symbols in the pseudo-pilot signals are assumed to be known. The method includes the steps of estimating the transfer functions using the pilot signals, carrying out interpolation coherent detection of the information symbols using the estimated transfer functions, storing the detection results as the pseudo-pilot signals, reestimating the transfer functions associated with the information symbols corresponding to the pseudo-pilot signals by using the pseudo-pilot signals and the corresponding received signal under the assumption that the pseudo-pilot signals have a known correct pattern, and carrying out the interpolation coherent detection of the individual information symbols by using the transfer functions obtained by the reestimation.