Abstract: An image compression coding method of a digital image transmission system utilizes a known vector quantization process.

Abstract: A transmission frame comprises a synchronization flag, synchronization bits and data bits. A control bit is substituted for one of the synchronization bits if any sequence of bits the same length as the synchronization flag including the synchronization bits differs from the synchronization flag by at least one bit in addition to the synchronization bit.

Abstract: A phase-locked-loop (PLL) has a current controlled oscillator (ICO) whose gain varies with its input current. The PLL also contains a charge pump that controls the input current of the ICO and therefore the output frequency of the ICO. The charge pump has a gain that is controlled by the ICO input current in a manner which linearizes the combination of charge pump and ICO. This results in a substantially constant loop gain for a PLL.

Abstract: A method voting multiple messages begins with a communication unit (111) transmitting (301) a message. At each of a plurality of sites, the message is received (303) and decoded (305) such that a minimized metric is computed and decoded message is extracted from the message. The minimized metric is adjusted (307), producing an adjusted metric. Each of the plurality of sites transports (309) its decoded message and its adjusted metric to a comparator. The comparator receives (311) selecting the decoded message and the adjusted metric from each of the plurality of sites, compares (313) selecting the adjusted metric from each of the plurality of sites and finds an optimal adjusted metric. The decoded message associated with the optimal adjusted metric is then selected (315).

Abstract: A data transmission link is especially designed to meet new FCC regulations setting 5 KHz band widths for transmitting control signals to industrial systems. The new band width creates timing distortions which are overcome by inserting a new timing pulse into a data pulse stream. The center of that inserted timing pulse is taken as an axis of reference for retiming each pulse in the data pulse stream so that the fluctuations of a time frame synchronizing pulse become irrelevant. The retiming process is repeated for each data time frame.

Abstract: The phase of a received signal is detected by a phase detector at symbol intervals T relative to the phase of a local signal. The detected phase is input to delay circuits that are connected in series and each of which has the delay interval T. Phases .PSI..sub.n (where n=0, 1, . . . , N) with delays of 1 to N symbols are output to a metric calculating portion. The sum of a partial sequence {.DELTA..phi..sub.i ; i=n+1-q, n+2-q, . . . , n} of a N-symbol phase difference sequence candidate {.DELTA..phi..sub.n ; n=0, 1, . . . , N} is added to a detected phase .PSI..sub.n-q at a time point (n-q)T (where q=1, 2, . . . , N) so as to obtain an estimated value of the received signal phase .PSI..sub.n. The v-th power value of the absolute value of a difference .mu..sub.n (q) between the estimated value and the received signal phase is defined as a branch metric of q-symbol differential phase detection. .SIGMA..vertline..mu..sub.n (q).vertline..sup.v =.lambda..sub.

Abstract: A method and apparatus for setting the parameters of an equalizer. Equalizers are used for equalizing distorted signals. However, optimum equalization is only achieved when the parameters of the equalizer are optimally set. To set the parameters of an equalizer optimally, the output signal of the equalizer is rectified in a full-wave rectifier. The output signal of the latter is integrated in an integrator. The parameters of the equalizer are set by a microprocessor according to an algorithm. In one embodiment, when the integration time is predetermined, the parameters of the equalizer is changed until the level of the integrated signal becomes a maximum. In another embodiment, when the maximum level of the integrated signal is predetermined, the parameters of the equalizer are changed until the integration time becomes a minimum.

Abstract: A binary phase shift keyed (BPSK) modulator (200) used for digital phase modulation is shown. Phase shift is achieved by electrically switching an RF input signal (201) through either a direct signal path (203) or through a half wave transmission signal path (205) to shift its phase by 180 degrees. Both the data signal (211) and its complement (213) are used to turn on one of PIN diodes (207, 209) while simultaneously turning off the other diode with reverse bias. This technique allows for obtaining maximum diode isolation. The BPSK modulator (200) has the advantages of very low insertion loss, dc coupling for low frequency modulation components and high performance with minimum parts.

Abstract: A method and apparatus for recovering a timing phase and frequency of a sampling clock signal in a receiver are disclosed for determining a desired timing phase by minimizing a mean squared error due to uncancelled precursor intersymbol interference. A detected symbol error is correlated with a signal obtained from the received signal. This correlation function provides an approximate of the time instant where the mean squared error approaches its minimum at which point an unambiguous zero crossing of the correlation function signal is obtained. From such an unambiguous zero crossing, e.g., only one zero crossing, a desired sampling timing instant is determined.

Abstract: A method and an apparatus for encoding a digital audio signal are provided. The method comprises the steps of: mapping the digital audio signal into a plurality of sub-bands and outputting the mapped sub-band signals; allocating a number of bits to each sub-band signal according to human psychoacoustic properties, on the basis of the mapped sub-band signals; compensating each sub-band signal by receiving a transmitted previous quantized error, quantizing the compensated sub-band signals according to the corresponding allocated bit number, and transferring the current quantized error to the next quantization; and forming a transmit bit stream in frame units from the quantized data. Therefore, the quantized error generated during encoding of the audio signal is can be minimized.

Abstract: A maximum likelihood sequence estimator implemented to cope with an intersymbol interference from a single symbol employs a necessary channel impulse response estimation vector of two components for a decision to estimate a maximum likelihood sequence. A channel impulse response estimator implemented to estimate a channel impulse response in consideration of intersymbol interferences from up to two symbols outputs a channel impulse response estimation vector of three components. The three-component vector is input to a converter, where it is converted into the two-component vector to be output to the maximum likelihood sequence estimator.

Abstract: Interference removal in spread spectrum signals, comprises the steps at a spread spectrum transmitter (10) of spreading information across a predetermined spectrum by phase modulating a repeating noise sequence (18), providing a spread spectrum signal and transmitting the spread spectrum signal. The method further comprises the steps at a receiver of receiving the spread spectrum signal along with interference (41) multiplying (42) the spread spectrum signal along with interference by a window function (44) providing a multiplied spread spectrum signal. The information is recovered by despreading the multiplied (48) spread spectrum signal using a reciprocal (50) of the spectrum of the repeating noise sequence to obtain a data spectrum with interference and subsequently normalize (52) to obtain a clean data spectrum. Alternatively the information can be recovered by substituting a corrupted magnitude spectrum with a prestored PN sequence magnitude spectrum (70) as shown by receiver (60).

Abstract: A clock recovery circuit comprises first and second voltage-controlled oscillators having identical characteristics. The first oscillator is incorporated into a frequency synthesis loop in such a way as to oscillate, in response to a first control voltage, at a frequency equal to a reference frequency multiplied by a number N. The second voltage-controlled oscillator is incorporated into a phase tracking loop which, when activated, locks its oscillation phase relative to that of the received data signal. The second oscillator delivers the recovered clock signal. A comparator determines whether the frequency of the second oscillator, divided by N, satisfies the condition of not deviating from the reference frequency by more than a predetermined limit value. The phase tracking loop is activated only when the latter condition is satisfied, and the first control voltage is fed to the control input of the second oscillator when the condition is not satisfied.

Abstract: A synchronous sampling data detection channel includes a data transducer head positioned by a servo-controlled actuator over a recording track of a rotating data storage disk, a preamplifier for receiving electrical analog signals magnetically induced by the data transducer head from flux transitions present in at least the servo information field, a digital sampler for synchronously sampling the electrical analog signals to produce digital samples, and a Viterbi detector coupled to receive digital samples from the synchronous sampling data detection channel for decoding 1/4 T coded wide biphase servo information patterns patterns as maximum likelihood servo data sequences, wherein the wide biphase magnet patterns are arranged e.g. as ++-- magnet patterns for a binary zero information value and --++ magnet patterns for a binary one information value.

Abstract: Method and apparatus for efficient encoding of symbols with multilevel encoding, where components of the symbols that are more susceptible to errors are encoded more robustly than components that are less susceptible to error. A non-binary constellation of symbols is handled with a fractional bit rate converter that combines with the multilevel encoder to create an effective and efficient constellation of symbols. Illustratively, digital data is encoded and mapped onto a set of symbols, with the two least significant bits of the symbols being encoded with a multi-level code. The least significant bit is encoded with a code that is more robust than the code of the next-to-least significant bit, in recognition of the fact that errors in the least significant bit are much more likely. The most significant bits are mapped with the aid of a fractional bit rate mapper that optimizes a selected aspect of the symbol constellation, such as average power.

Abstract: A device and method for receiving a radio signal transmitted over a channel, selecting and deselecting an equalizer, and balancing processing in response to such selection. A radio frequency signal is received from a transmission channel into a receive path, and delay spread in the radio frequency signal is estimated using an analysis circuit. The analysis circuit also determines a threshold delay spread. In the event the estimated delay spread exceeds the threshold delay spread, an equalizer is selected, otherwise the equalizer is deselected. Similarly, in the event the estimated delay spread does not exceed the threshold delay spread, a high complexity processor is selected, otherwise a low complexity processor is selected. If the low complexity processor is selected, an output signal is generated using the low complexity processor, and if the high complexity processor is selected, the output signal is generated using the high complexity processor.

Abstract: A phase synchronizer is disclosed that provides a stable output signal while improving synchronization speed. The phase synchronizer includes one or two feedback circuits. The feedback circuit(s) includes a phase comparator for generating a pulse signal in accordance with a difference between the phases of an input signal and a feedback signal, a charge pump for converting the pulse signal supplied from the phase comparator to an analog voltage signal, a loop filter for removing high-frequency signal components from the analog voltage signal output from the charge pump and supplying as a filtered analog voltage signal (LF1 or LF2), and a voltage-controlled oscillator coupled to the loop filter for generating an oscillation output signal having a frequency which varies in accordance with the filtered analog signal (LF1 or LF2). The oscillation output signal is also supplied as the feedback signal to the phase comparator.

Abstract: A signal transmission system (10) is provided that comprises a transmitter circuit (12) which transmits a signal through a transmission line (16) to a receiver circuit (14) using the current mode of signal transmission. A steady state current is supplied by a steady state current source (22). An active state current is provided by an active current source (20). A boost circuit (18) is provided to reduce delay associated with the transmission line (16) by increasing charge to the transmission line and providing additional discharge path from the transmission line during transitions of the signal propagating along transmission line (16).

Abstract: An apparatus for generating a pulse clock signal for a multiple-stage synchronizer provides a pulse clock signal to a synchronizer. The synchronizer synchronizes data received in a first clock domain, which is referenced to a first clock signal, to a second clock domain, which is referenced to a second clock signal. The apparatus includes a synchronization pulse generator and a multiplexer. The synchronization pulse generator generates a synchronization pulse based on the first clock signal and the second clock signal. The multiplexer outputs one of either the first clock signal or the synchronization pulse as the pulse clock signal based on an input control signal.

Abstract: A digital phase-locked loop adjusts the phase of a Recovered Clock in the receiver under the condition of asynchronous serial data transmission so that the phases of the transmission data are locked in order to reduce errors in read data. The digital phase-locked loop includes a zero-phase start circuit, a phase-error detecting circuit, an error-filtering circuit, a Recovered Clock adjusting circuit and a clock-generation circuit. This phase-locked loop generates a set of clocks through the detection of the transmission data level in the zero-phase start circuit so as to lock the phase of the transmission data quickly, and the phase-error detecting circuit detects the phase error between the phase of the transmission data and the phase of the Recovered Clock, after which the phase error signal is filtered through the adaptive filtering circuit for conversion into error-adjusting signals.