Abstract: A discriminator provides an output signal having an amplitude proportional to the frequency of a measured signal. The output of the discriminator is connected to a differentiator circuit that provides an impulse signal proportional to a cycle to cycle frequency change of the measured signal.

Abstract: A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

Abstract: A spread spectrum communication apparatus for communication with a plurality of communication units includes a reception circuit, an automatic gain control circuit, a spread spectrum code detection circuit, and a synthesis circuit. The reception circuit receives signals of a frequency channel inclusive of a target communication unit. The automatic gain control circuit controls the signal intensity of the frequency channel received by the reception circuit to a constant level. The spread spectrum code detection circuit detects the signal intensity of the spread spectrum code of the target communication unit from an output signal of the automatic gain control circuit. The synthesis circuit combines the signal intensity which is based on a gain control signal of the automatic gain control means with a signal intensity as detected by the spread spectrum code detection circuit to find a reception intensity.

Abstract: A hybrid analog-digital phase error detector (107) is utilized for detecting a phase error between first and second clock signals (132, 104). Digital and analog phase error detectors (108, 116) are connected to the first and second clock signals (132, 104), and are utilized for producing digital and analog phase error values (110, 118). The digital and analog controllers (112, 120) connected to the digital and analog phase error detectors (108, 116) execute digital and analog control algorithms based on the digital and analog phase error values (110, 118) to produce digital and analog control signals (114, 122). A summer (124) connected to the outputs of the digital and analog controllers (112, 120) combines the analog control signal (122) and the digital control signal (114) to produce a composite control signal (126) representing the phase error.

Abstract: A PLL based microprocessor whose frequency may be adjusted by using a microprocessor clock control circuit. The microprocessor clock control circuit comprises a circuit for providing a slew rate limited overdampened PLL that continuously seeks a new frequency, a circuit for selecting a current target frequency for the microprocessor, a circuit for comparing the current target frequency to the current frequency setting of the microprocessor, and a circuit for adjusting the current frequency setting of the microprocessor to match the current target frequency.

Abstract: An inversion prevention device to prevent inversion and provide the best S/N ratio detects a point where the zero crossing is missing from a quantized FM signal. An output is provided by switching between the digital FM signal and the output signal of at least one sideband suppression filter based on a result of the inversion detection. Alternatively, an output is provided by switching between the digital FM signal and a specified value based on a result of the inversion detection. As a further alternative, an output is provided by switching between the digital FM signal, the output signal of a low-sideband emphasis filter and the output signal of a sideband suppression filter based on a result of the inversion detection.

Abstract: A communication system for sending a sequence of symbols on a communication link. The transmitter receives a sequence of symbols and groups the symbols into a block of symbols for which transmission is to be initiated in a following frame. Each symbol is used to modulate a different carrier. At the receiver, the signal from the communication link is decoded by a plurality of finite impulse response (FIR) filters that are matched to the waveforms modulated by the symbols in the transmitter. Errors arising from synchronization errors between the transmitter and receiver are corrected by forming weighted sums of the symbols decoded by the FIR filters for the current frame and frames received prior to and/or after the current frame. The weights are determined by training samples sent on the communication link prior to the actual transmissions.

Abstract: A method adapts the amount of messages with a number of various identities transferred between a transmitter and a receiver. The transfer is accomplished in such a way that no essential information is lost even if the message rate from the transmitter exceeds the possible transfer rate. A data area is created in which each message with a certain identity is stored while awaiting to be transferred. When a new message with the same identity as an earlier stored message is supplied to the data area, the new message replaces the earlier stored message. The messages stored in the data area are scanned and are transferred to the receiver at a rate which is adapted to the rate possible for the transfer.

Abstract: There is disclosed a spread code generation device for spread spectrum communication wherein an input data is modulated so as to be spread by a spread code having a first period. The device includes a long period PN code generator for generating a spread code having a second period longer than the first period, an initial state register for storing an initial phase of the spread code having the first period output from the long period PN code generator and for outputting the initial phase to the long period PN code generator, and a counter for receiving and computing the spread code output from the long period PN code generator and for outputting a trigger signal to the initial state register when the computed spread code reaches the first period. The initial state register outputs the initial phase to the long period PN code generation in response to the trigger signal from the counter.

Abstract: In a radio transmission output control circuit, a modulating circuit modulates signals to be sequentially transmitted in consecutive time slots at predetermined timings. A data generating circuit generates, when one time slot is being transmitted, data meant for another time slot to be transmitted subsequently. The data include output control information for the subsequent time slot, and the deviation of the output level of the subsequent time slot. The data generating circuit outputs the data at a transmission timing assigned to the subsequent time slot. A level control circuit controls the output level of the subsequent time slot on the basis of the data from the data generating circuit. With this configuration, it is possible to execute control over a transmission output signal rapidly.

Abstract: The present invention provides linear, digital automatic gain control (AGC) in a radio. A received signal is demodulated to provide I and Q digital baseband signals. A received signal strength indication is determined from these signals and the resulting digital signal is adjusted to provide a logarithmic response. This signal is then integrated to provide a digital receive AGC adjust signal. For the transmit AGC adjust, the digital receive AGC adjust signal is filtered and then summed with a scaled closed loop power control command. The closed loop power control commands are ignored if they would result in increasing the transmit gain beyond the amplifier's designed maximum output. The result of the sum operation converted from digital to analog for adjusting the amplifier. The outputs of the transmit and receive AGC amplifiers are linearized by transmit and receive linearizers, respectively, which pre-distort the digital AGC adjust signals prior to digital to analog conversion.

Abstract: A synchronous adder device comprising an A/D converter for digitizing a receive signal transmitted through a plurality of subcarriers by sampling it and an adding unit for determining the value of synchronous addition for each sample is provided with synthetic waveform shaping filters for waveform-shaping every other subcarrier, squaring units for squaring the respective outputs of the synthetic waveform shaping filters, and a low pass filter for removing a harmonic components from the sum of outputs of the squaring units. In the case where the signal is transmitted through four subcarriers, synchronous addition becomes possible by using the synthetic waveform shaping filters the number of which is two for each of an I signal and a Q signal or is four in total. The number of squaring units equal to the number of synthetic waveform shaping filters suffices.

Abstract: The present invention provides a novel method, device, digital signal processor and modem for efficiently determining and tracking a phase roll of a far end echo by utilizing a novel phase error generator and a novel, efficient replica generator. The efficient replica generator utilizes a uniquely positioned phase rotator to facilitate replication of the far end echo. A unique combination of a Hilbert phase splitter and a conjugate Hilbert phase splitter together with a rectangular to polar converter enable the novel phase error generator to provide a reliable phase error.

Abstract: A rotationally invariant trellis coder is provided for encoding data to be transmitted using a two-dimensional symbol modulation. A precoder, provided at the transmitter, processes data such that a counterpart postcoder at the receiver will provide an output that is invariant to any multiple of a 90.degree. rotation. An encoder encodes the precoded data using a transparent binary convolutional code, which can be a punctured or unpunctured code. The encoded data is mapped to a two-dimensional signal space having a plurality of signal points. The signal points are labeled with unique binary codes in which the two least significant bits, denoted by (I.sub.j, Q.sub.j), are permuted and partially complemented to (Q.sub.j, I.sub.j) for each 90.degree. phase rotation around the signal space. The remaining most significant bits for each point, if any, are invariant to such rotation. The postcoder provided at the receiver inverts the precoder and is feedback-free, thus limiting error propagation.

Abstract: A system and method for adaptively sectorizing channel resources within a digital cellular communication system is disclosed herein. The system includes an antenna arrangement for providing at least first and second electromagnetic beams for receiving a first information signal transmitted by a specific one of a plurality of users, thereby generating first and second received signals. A first set of beam-forming signals are then generated from the first and second received signals. A demodulating receiver is provided for demodulating at least first and second beam-forming signals included within the first set of beam-forming signals, thereby producing first and second demodulated signals. The system further includes a tracking network for tracking multipath information signals, received from various positions and angles of incidence, based on comparison of the first and second demodulated signals.

Abstract: A satellite communication system (10) includes at least one satellite communication signal repeater (12); at least one ground station (18) for transmitting a feeder link comprised of a plurality of communication signals to the at least one satellite communication signal repeater; and a plurality of user terminals (13) each receiving one of the communication signals over a user link from the at least one satellite communication signal repeater. The satellite communication system further includes a closed loop power control system (80) having a plurality of inner loops (84), individual ones of which operate to compensate one of the user links for communication signal impairments occurring at least between the user terminal and the at least one satellite communication repeater, and an outer loop (82) which operates to compensate all of the user links for feeder link impairments occurring between the at least one ground station and the at least one satellite communication signal repeater.

Abstract: An interface method and device in a digital signal processing system which stores digital data regenerated from a recording unit in a memory, reads the digital data from the memory in response to a data transmission request signal of an object interface part, and transmits the read digital data to the object interface part in units of sound groups and also transmits channel classification data of 1 byte to classify the channel of the transmitted data together with the digital data to the object interface part.

Abstract: A frequency control circuit for a receiver of phase shift keying (PSK) modulated signals comprises intermediate frequency (IF) signal generation circuit for generating an IF signal from a local oscillation signal. A measurement circuit measures the frequency of the IF signal. A detection circuit detects the frequency shift due to the PSK modulation to output a frequency shift signal in response to a first control signal. A control circuit detects that the frequency of the IF signal is converged until the detection circuit can detect the frequency shift due to the PSK modulation.

Abstract: Apparatus and methods for improving timing recovery of a system clock by causing its frequency to be within a specified tolerance range during a timing recovery acquisition period for the system clock. The apparatus includes a voltage controlled oscillator for producing the system clock and a non-volatile memory containing an offset value. The non-volatile memory provides an offset value (representing an offset voltage value) which assures that the voltage controlled oscillator receives a voltage value which causes the frequency of the system clock to be within a specified tolerance range. The apparatus may also include a write control unit for determining and updating the offset value for a next timing recovery acquisition period. The methods include steps for performing these operations.

Abstract: A synchronization signal generation device includes a circuit that enables a phase difference between a synchronization signal and an input signal with intermittent edges to be arbitrarily and continuously varied. The synchronization signal generating device is of the second order phase locked loop and has a phase detector with the following elements: a circuit for generating pulses with widths corresponding to the phase difference between the input signal and the synchronization signal only upon occurrence of an edge of the input signal; a circuit for generating pulses with a constant width only upon occurrence of an edge of the input signal or the synchronization signal; a variation circuits which varies one or both of the amplitudes of the aforesaid pulses; and a combining circuit which adds or subtracts the pulses from the variation circuits to derive a phase comparison signal.