Abstract: It is intended to provide a semiconductor device, its manufacturing method and substrate for manufacturing the semiconductor device which ensures that good cleavable surfaces be made stably in a semiconductor layer under precise control upon making edges of cleaves surfaces in the semiconductor layer stacked on a substrate even when the substrate is non-cleavable, difficult to cleave or different in cleavable orientation from the semiconductor layer. A semiconductor layer 2 made of III-V compound semiconductors is stacked to form a laser structure on a sapphire substrate 1.

Abstract: A semiconductor device comprising; two rectangular semiconductor chips, each function of which is different from each other; two die pads, a plurality of leads for carrying either of the two die pads, each of the plurality of leads being supported by a lead frame and being connected to either of the two die pads; a plurality of leads for connecting either of the two semiconductor chips with any of outer connection terminals; a package in which the two semiconductor chips are encapsulated; wherein the leads for carrying are provided at larger side faces of the package and at smaller side faces of the package; and wherein each of the two die pads is supported at at least three side faces of the package.

Abstract: In the step of forming a microcrystalline i-type semiconductor layer by high-frequency plasma CVD, wherein an area of the parallel-plate electrode is represented by S; a width of the discharge space in its direction perpendicular to the transport direction of the belt-like substrate, by Ws; a width of a region formed by the parallel-plate electrode together with its surrounding insulating region, in its direction perpendicular to the transport direction of the belt-like substrate, by Wc; a width of the belt-like substrate in the direction perpendicular to its transport, by Wk; a distance between the parallel-plate electrode and the belt-like substrate, by h; a power density at which crystal fraction begins to saturate at predetermined substrate temperature, material gas flow rate and pressure, by Pd; and a high-frequency power, by P, 2h/(Ws−Wc)≧2.5, (Ws/h)×2(Ws−Wk)/[4h+(Ws−Wc) ]≧10, and P≧(10/8)×Pd×S.

Abstract: A semiconductor device having a registration accuracy measurement mark allows measurement in registration to be within an allowable measurement error even if there is a difference in height between a master pattern and a pattern of the registration accuracy measurement mark. The width of the second layer registration accuracy measurement mark pattern formed as a line is made larger than that of the second layer master pattern formed as a line by 0.85 &mgr;m to 1.0 &mgr;m. Accordingly, the difference in the amount of offset due to aberration upon transfer of the patterns between the second layer master pattern and the second layer registration accuracy measurement mark pattern can be within an allowable range in the overlay measurement. In addition, even if the second layer registration accuracy measurement mark pattern and the second layer master pattern are formed to have a difference in height (maximum 0.6 &mgr;m), the depth of focus (1.2 &mgr;m) is ensured.

Abstract: A semiconductor device of the present invention includes a semiconductor chip with bumps on a surface, and an adhesion sheet on the surface of semiconductor chip. The adhesion sheet has a film base material layer and a film adhesion layer for adhering the film base material layer to the semiconductor chip, and a part of the sheet melts upon heating and tears in response to pressure applied during flip chip bonding. Therefore, it is possible to obtain a semiconductor device which enables good flip chip bonding without any gaps between a device and a substrate in a simple manufacturing process, and to manufacture the semiconductor device.

Abstract: A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable.

Abstract: A semiconductor quantum oscillation device, which realizes Bloch oscillation on the basis of a novel carrier injection scheme, comprises a multilayer semiconductor structure and a means for applying a voltage to said structure. The multilayer structure comprises a tunneling injection region and a pair of oscillation regions which are located on both sides of the tunneling injection region and adjacent to it. The voltage applied across the tunneling region and the pair of oscillation regions causes valence electrons to enter into the conduction band through interband tunneling in the tunneling injection region and leads to electrons and holes being injected into the pair of oscillation regions, respectively. The electrons and holes injected this way undergo quantum oscillation motion and produce far-infrared radiation. The device of the present invention will pave the way for effectively utilizing the electromagnetic spectral resource between the high-end of millimeter-wave and the low-end of far infrared.

Abstract: A quantum computer comprising a semiconductor substrate into which donor atoms are introduced to produce an array of donor nuclear spin electron systems having large electron wave functions at the nucleus of the donor atoms, where the donor electrons only occupy the nondegenerate lowest spin energy level. An insulating layer above the substrate. Conducting A-gates on the insulating layer above respective donor atoms to control strength of the hyperfine interactions between the donated electrons and the donor atoms' nuclear spins, and hence the resonance frequency of the nuclear spins of the donor atoms. Conducting J-gates on the Insulating layer between the A-gates to turn on and off electron mediated coupling between the nuclear spins or adjacent donor atoms.

Abstract: A lead frame assembly including at least two layers. A first of the lead frame layers includes a first wide, electrically conductive bus and a plurality of leads that extend substantially unidirectionally from a single edge of the lead frame assembly. The second lead frame layer includes a second wide, electrically conductive bus that is superimposed over the first bus and a plurality of lead fingers extending substantially unidirectionally from a single edge of the lead frame assembly. Preferably, the lead fingers of both the first and second layers extend in substantially the same direction. An insulator element is disposed between the first and second buses. One of the buses is connectable to a power supply source (VCC), while the other is connectable to a power supply ground (VSS). Thus, the co-extensive portions of the first and second buses form a decoupling capacitor.

Abstract: Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative material interposed therebetween. A potential supplied to the pad positioned at the outer peripheral portion can be stabilized by parasitic capacitance of the die pad, and a potential of the die pad can be externally monitored easily by removing away a portion of mold resin after resin sealing. Further, due to a cress shaped arrangement of the pads, a voltage down converter can be arranged in line with the pads and at outer periphery of the chip without area penalty. In testing operation, a switching circuit switches a function of a pad to another pad so that cross-shapedly arranged pads are equivalently arranged in a line.

Abstract: A programmable interconnection system and methods of forming interconnections in the system are disclosed. The system generally includes a metal doped chalcogenide pathway. A metal feature is created within the system by applying a voltage bias across the chalcogenide pathway.

Abstract: Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a bottom of the trench region and in a surface of the substrate adjacent to the trench region and in contact with the channel region, and gate electrodes at sides of the trench insulated from the trench wall.

Abstract: A multi-chip module (“MCM”) and methods of operation and manufacture thereof. The MCM includes: (1) a substrate for supporting a plurality of separate integrated circuit (IC) chips thereon, (2) first and second separate IC chips mounted on the substrate, the first separate IC chip including first and second circuit portions coupled together by at least one signal conductor, and (3) interconnecting means that directly couples at least one signal conductor of the first separate IC chip to the second separate IC chip, the interconnecting means bypassing the second circuit portion of the first separate IC chip.

Abstract: A semiconductor light emitting device easily controlled in reflectance of its cavity edges has formed on the cavity edges of its laser cavity rugged structures including elongated concave portions extending substantially in parallel with bonded surfaces of semiconductor layers forming the laser cavity. The laser cavity is made by sequentially stacking on a substrate an n-type AlGaN cladding layer, n-type GaN optical guide layer, InGaN active layer, p-type GaN optical guide layer and p-type AlGaN cladding layer. The rugged structure is made by first making the cavity edges by etching and then processing the cavity edges by wet etching so that the cavity edges are selectively excavated due to differences in chemical property among semiconductor layers forming the laser cavity caused by differences in composition among them.

Abstract: A thin film transistor and a method for fabricating the same are disclosed, in which an offset region is affected or biased by a gate voltage to increase on-current, thereby improving on/off characteristic of a device. A first semiconductor layer is formed on a substrate, and insulating layer patterns are formed at both ends of the first semiconductor layer. A second semiconductor layer is formed on the first semiconductor layer and the insulating layer patterns. A gate insulating film is formed on the first and second semiconductor layers and the insulating layer patterns, and an active layer formed on the gate insulating film.

Abstract: A QFN semiconductor package comprises a semiconductor die, a lead frame, bonding wires and a molding compound. The die has an upward topside with a plurality of bonding pads. The lead frame consists of a plurality of inner leads, wherein each inner lead is divided into the front finger portion, the middle protruding portion and the rare connecting portion. The front finger portion is the position of the inner lead to which a bonding wire wire-bonds from the bonding pad of the die. The rare connecting portion is for the electrical out-connection of the package. The middle protruding portion is at height level higher than the front finger portion and the rare connecting portion. The bonding wires electrically connect the bonding pads of the die with the front finger portions of inner leads by means of wire-bonding.

Abstract: A case (3) of a photointerrupter (A) includes a pair of projections (35) for preventing a light source (1) and a photodetector (2) from coming out of a respective one of paired receiving portions (30). Each of the projections (35) is connected to a respective first wall (32A) defining the respective receiving portion (30) of the case on an extension line of a respective slit (34) for light transmission. Therefore, the case (3) need not be formed with a large slit other than the slit (34), so that disturbing external light is less likely to enter the receiving portions (30).

Abstract: A method is shown for producing a PIN photodiode having low parasitic capacitance and wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A first glass layer is formed on a first surface of a handling substrate. The first surface of the handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication substrate is then lapped to a obtain a preselected thickness of the intrinsic layer. A second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate.

Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferable, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.