Abstract: A light emitting diode in accordance with the present invention has a p-n junction which is formed by selectively implanting an impurity from the surface of a semiconductor substrate, and also has an etched groove which is formed in the p-n junction area near the surface of the substrate. In the area where the etched groove is formed, the p-type area and the n-type area are spatially separated in the region of the substrate, therefore the movement of minority carriers does not occur. As a consequence, in the light emitting diode in accordance with the present invention, the movement of minority carriers in the p-n junction interface occurs at a deeper position of the semiconductor substrate. In a deep position of the semiconductor substrate, the recombination rate of minority carriers is high. Therefore if the recombination of minority carriers is increased in a deep position, the emission efficiency of the light emitting diode increases.

Abstract: The present invention is directed toward an apparatus and method of reinforcement of lead bonding in microelectronics packages. In one embodiment, a microelectronics package includes a microelectronics device having a bond pad, a conductive lead having a first end bonded to the bond pad to form a lead bond, an encapsulating material at least partially disposed about the conductive lead, and a reinforcement portion at least partially disposed about the lead bond and at least partially coupling the first end to the bond pad. The reinforcement portion has a greater modulus of elasticity and/or a greater bond strength than the encapsulating material.

Abstract: A method of manufacturing a semiconductor device including the steps of (a) forming an element isolation insulating film in an element isolation region of a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order, and (b) forming, in an element formation region of the SOI substrate, a transistor having a channel formation region selectively disposed in a main surface of the semiconductor layer, a gate structure on the channel formation region, and source/drain regions disposed is the main surface of the semiconductor layer and the adjacent channel formation region. The method also includes the step of (c) selectively growing, after said steps (a) and (b), a polycrystal semiconductor layer on the source/drain regions in a self-aligned manner, which is prescribed by the element isolation insulating film and the gate structure.

Abstract: A leadless semiconductor package mainly comprises a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. The lower surface of each lead has an indentation formed corresponding to one of the bottom edges of the package. The semiconductor chip, the leads and the tie bars are encapsulated in a package body wherein the lower surface of each lead is exposed from the bottom surface of the package except the indentation thereof.

Abstract: A semiconductor device with a gate spacer containing a conductive layer, and a manufacturing method. A first spacer insulation layer is formed on a semiconductor substrate where a gate electrode is formed. Then, the first spacer insulation layer is etched to cover the side walls of the gate electrode. A conductive spacer film is subsequently formed on the resultant structure and is over-etched to form a conductive spacer that covers the first spacer insulation layer. In this step, the gate electrode is partially consumed to make the top of the first spacer insulation layer higher than the gate electrode. Also, an upper portion of the first spacer insulation layer is not comparatively etched due to an etching selectivity. This structure avoids shorts between the conductive spacer and the gate electrode. A second spacer insulation layer is then formed on the conductive spacer.

Abstract: A multi-chip module (MCM) that fails testing after its assembly is repaired by generating a wire-bonding solution for a repair die during testing, storing the repair solution in a computer system in association with a unique ID code read from the MCM, and then using the repair solution at a wire-bonding station to correctly bond out a repair die for the MCM. The use of a stored repair solution at the wire-bonding station eliminates the need for a human operator to manually select the repair solution, and thus reduces the opportunity for error while shortening the length of time it takes to complete the repair process.

Abstract: A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

Abstract: A semiconductor package is disclosed. According to one embodiment, the package comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a metal layer above the reference layer and traces on a metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connect to the solder balls through vias and possibly through routing on another metal layer.

Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes at least one and preferably two capacitor electrodes for making both types of interconnects. A method for making the DRAM memory cell includes forming one or more capacitor electrodes at the same time the electrodes of the storage capacitor of the memory cell are formed, and from the same material as the storage capacitor electrodes.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the undersides of the lead elements proximate the adhesive to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The increased space created by the slots and flexure in the leads about the slots reduces point stresses on the active surface of the die by the filler particles. The increased flexure in the leads about the slots further enhances the locking of the leads in position with respect to the die.

Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.

Abstract: A field oxide surrounding an active region, an N-type doped layer formed in the active region, and an electrode formed on the field oxide in the vicinity of the active region are provided on a P-type semiconductor substrate. During the operation as a constant voltage device, a desired voltage is applied to the electrode. Then, trapping of carriers in the interface between the field oxide and the semiconductor region can be suppressed, although such trapping is ordinarily caused by a reverse breakdown phenomenon at the pn junction between the doped layer and the P-type semiconductor substrate. Accordingly, the variation in strength of the electric field between the doped layer and the semiconductor substrate can be suppressed. As a result, it is possible to suppress a variation in reverse withstand voltage, which is usually caused by a reverse breakdown voltage at a pn junction, for a semiconductor device functioning as a constant voltage device.

Abstract: With a housing for accommodating a planar power transistor, a chip of the power transistor is arranged hermetically sealed inside the housing, and metallized areas on the chip lead out of the housing by way of electric terminals. At least in some areas, the housing is formed by at least one of the electric power terminals.

Abstract: A flexible substrate based BGA package mainly comprises a semiconductor chip securely attached onto a flexible film substrate through a nonconductive adhesive. The flexible film substrate is formed from a flexible film having a chip attaching area for carrying the semiconductor chip. The upper surface of the flexible film is provided with a plurality of chip connection pads, a plurality of solder pads, and at least a dummy pad which is disposed centrally on the chip attaching area. The purpose of the dummy pad is to increase the rigidity and strength of the central part of the chip attaching area. The chip connection pads are arranged about the periphery of the chip attaching area for electrically connected to the semiconductor chip. The solder pads are disposed about the dummy pad(s) and electrically connected to the corresponding chip connection pads.

Abstract: This invention discloses a semiconductor device which comprises a thin semiconductor substrate; first and second word lines formed on the thin semiconductor substrate; a first source, a common drain and a second source formed on the thin semiconductor substrate; a bit line connected to the common drain; a first capacitor formed in front of the thin semiconductor substrate, with the first capacitor having a first charge storage electrode connected to the first source, a first dielectric film and a first plate electrode; and a second capacitor formed in reverse side of the thin semiconductor substrate, with the second capacitor having a second charge storage electrode connected to the second source, a second dielectric film and a second plate electrode.

Abstract: A crystalline silicon film is formed on a substrate containing OH group at 50-2,000 ppm and chlorine at 10-1,000 ppm at a process temperature range of 640°-980° C. by utilizing nickel. A thermal oxidation film is formed on the crystalline silicon film at a process temperature within the above range in an atmosphere containing HCl. By virtue of the action of chlorine, nickel is gettered into the thermal oxidation film. By removing the thermal oxidation film, a crystalline silicon film is obtained which has superior crystallinity and a low nickel concentration.

Abstract: In a mounting structure of a flip chip IC, the flip chip IC is mounted on an alumina laminated substrate through conductive lands of the substrate and bumps of the flip chip IC. A space between the flip chip IC and the substrate is filled with resin. Further, inspection lands are provided on the substrate for inspecting the flip chip IC, and are electrically connected to the conductive lands through vias and inside wires provided in the substrate. That is, the inspection lands are connected to the conductive lands to bypath an edge portion of the resin. As a result, separation of the resin from the substrate can be prevented.

Abstract: Semiconductor light-emitting devices and methods for their manufacture using an efficient reflector to minimize optical loss due to the substrate absorption. The reflector comprises a plurality of discrete quarter-wave stacks deposited on a patterned substrate, allowing for current injection around the discrete reflector stacks. The reflector is further characterized by a high refractive-index ratio suitable for broadband high-reflectance applications of the light-emitting device.

Abstract: A field effect transistor includes (a) a semi-insulating GaAs substrate, (b) a step-doped structured active layer including an n type GaAs layer deposited on the substrate, and an n− type GaAs layer or a non-doped GaAs layer deposited on the n type GaAs layer, the n− type GaAs layer or non-doped GaAs layer being formed with at least one recess, and (c) a gate electrode formed in the recess so that the gate electrode is oriented in such a direction that drain current runs in the active layer along crystal orientation [01(−1)]. The field effect transistor enhances linearity of transfer conductance, and further improves strain characteristic.

Abstract: A method of forming an insulating film on a surface of a substrate includes the steps of heating the substrate in a processing chamber in an atmosphere containing water vapor maintained at 900° C. or higher to form a first insulating film on a surface of the substrate; and cooling down the substrate in the presence of water vapor to a temperature of 600° C. or less at a temperature decreasing rate of 15° C./sec or more so as to limit a thickness of a second insulating film formed at an interface between the first insulating film and the substrate.