Abstract: A multispectral radiation detector for detecting radiation in at least two spectral bands, comprises a substrate and a layer stack grown on the substrate. The layer stack comprises at least first and second photodiodes, each photodiode having at least one strain-compensating superlattice absorbing layer substantially lattice matched to adjacent layers of the detector. Each strain-compensating superlattice absorbing layer has an energy gap responsive to radiation energy in a corresponding spectral region and different from the energy gaps of other strain-compensating superlattice absorbing layers of the detector.

Abstract: A capacitor comprising a first electrode, a second electrode, and a dielectric material and an organic isolation matrix forming at least one layer between the first and second electrodes is provided. Also provided are other integrated circuit devices containing a dielectric material and an organic isolation matrix in contact with the dielectric material.

Abstract: It is intended to provide a semiconductor device, its manufacturing method and substrate for manufacturing the semiconductor device which ensures that good cleavable surfaces be made stably in a semiconductor layer under precise control upon making edges of cleaves surfaces in the semiconductor layer stacked on a substrate even when the substrate is non-cleavable, difficult to cleave or different in cleavable orientation from the semiconductor layer. A semiconductor layer 2 made of III-V compound semiconductors is stacked to form a laser structure on a sapphire substrate 1.

Abstract: The present invention provides an SOI device preventing the floating body effect, and a method for manufacturing the same. Disclosed is a method comprising the steps of: forming an isolation layer on a first silicon substrate; forming a conductive layer on the isolation layer and the first silicon substrate; forming a buried insulating layer on the conductive layer; bonding the second silicon substrate so as to contact with the buried insulating layer; exposing the isolation layer by removing backside of the first silicon substrate by selected thickness thereby defining a semiconductor layer; forming a transistor by forming a gate electrode, a source region and a drain region at selected portions of the semiconductor layer; etching a selected portion of the isolation layer so as to expose the conductive layer; and forming a body electrode to be contacted with the conductive layer within the isolation layer.

Abstract: A semiconductor device comprising an active layer made from a crystalline silicon formed on a substrate having an insulating surface; a gate insulating film formed on said active layer; and a source region and a drain region provided in contact with said active layer; wherein, said active layer generates photo carriers upon irradiation of a light, a part of the thus generated photo carriers having the opposite polarity with respect to that of the carriers flowing in the vicinity of the interface with the gate insulating film is temporarily accumulated within said active layer to change the resistance of the region of said active layer, and the light irradiated to said active layer is detected from the change in current flow between the source and the drain which occurs in accordance with the change in resistance in the region of said active region.

Abstract: A sparse-carrier device including a crystal structure (10) formed of a first material and having a crystallographic facet (26) with a width (w) and a length and quantum dots (30) formed of a second material and positioned in at least one row on the crystallographic facet (26). The at least one row of quantum dots (30) extends along the length of the crystallographic facet (26) and is at least one quantum dot (30) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet (26). The row of quantum dots (30) form a building block for circuits based on sparse or single electron devices.

Abstract: A synapse element consisting of a smaller number of elements utilizing common semiconductor technology, and a neuron circuit and a neuron device using the synapse elements are provided. The synapse element comprises a transistor set consisting of two MIS transistors connected in series. The first transistor adjusts the effective &bgr;-value of the transistor set so as to correspond to the weight factor &ohgr; via voltage applied to its gate electrode, and the second transistor switches the current according to input voltage to its gate electrode, so that output of the transistor set represents synapse output &ohgr;X. A voltage holding element and a switching element furnished to the gate of the first transistor give the neuron device a learning ability.

Abstract: Nitrogen-containing III-V alloy semiconductor materials have both a conduction band offset &Dgr;Ec and a valence band offset &Dgr;Ev large enough for the practical applications to light emitting devices. The semiconductor materials are capable of providing laser diodes, having excellent temperature characteristics with emission wavelengths in the red spectral region and of 600 nm or smaller, and high brightness light emitting diodes with emission wavelengths in the visible spectral region. The light emitting device is fabricated on an n-GaAs substrate, which has the direction normal to the substrate surface is misoriented by 15° from the direction normal to the (100) plane toward the [011] direction. On the substrate, there disposed by MOCVD, for example, are an n-GaAs buffer layer, an n-(Al0.7Ga0.3)0.51In0.49P cladding layer, an (Al0.2Ga0.8)0.49In0.51N0.01P0.99 active layer, a p-(Al0.7Ga0.3)0.51In0.49P cladding layer, and a p-GaAs contact layer.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Abstract: A semiconductor photonic device includes a substrate having a cleavage plane perpendicular to a principal plane thereof; a ZnO film on the substrate; and a compound semiconductor layer expressed by InxGayAlzN (x+y+z=1, 0≦x≦1, 0≦y ≦1, 0≦z≦1).

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: When both a wafer transfer means in a first transfer device and a wafer transfer means in a second transfer device move downward at the same time, the amount of exhaust air by an exhaust fan is increased by the control of a control section, whereby the down flow of clean air is intensified. Turbulence of air flow caused when both the wafer transfer means in the first transfer device and the wafer transfer means in the second transfer device move downward at the same time is absorbed by the down flow intensified as described above.

Abstract: This invention relates to a pressure-contact type semiconductor device (1) having a ring-shaped gate terminal, and aims at overcoming such a technical problem that a gate current is not uniformly supplied to a semiconductor substrate (4) due to a connection structure for the device (1) and an external gate driver (2). For this purpose, a ring-shaped gate terminal (10) is structured as a resistor whose resistivity is at least 0.1 m&OHgr;·cm in the present invention. Thus, a voltage drop by the aforementioned resistor enlarges in a concentrated part of the gate current, and it follows that the gate current is shunted to another non-concentrated part. The present invention is utilizable as a high-power element in a power applied device.

Abstract: A surface-emitting light-emitting diode having increased light emission is provided.

Abstract: A method and structure for a programmable circuit that includes a magnetic device having a reluctance which is alterable. The magnetic device can be programmed into one of three magnetic field orentations or states. Conventional VLSI fabrication steps are used for compatability with low-k dielectric Back-End-Of-Line (BEOL) processing.

Abstract: Contact holes which reach source/drain regions shared by access transistors and driver transistors are formed in a self-alignment manner with a silicon nitride film for covering gate electrodes. Therefore, contact plugs formed in the contact holes have an L plan shape. As a result, a semiconductor device including an SRAM can be obtained in which the transistor performance of both the access transistors and the driver transistors is improved and the difference in voltage dependence properties between the driver transistors and the load transistors is improved.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming both a p-well region and an n-well region at a surface of a semiconductor substrate, and (b) forming an n-type epitaxial layer on both the p- and n-well regions so that the n-type epitaxial layer contains impurities therein at a concentration lower than a concentration of impurities contained in the n-well region. For instance, the n-type epitaxial layer is formed by chemical vapor deposition in which a process gas including phosphorus or arsenic compounds therein is used. In accordance with the method, it is possible to optimize threshold voltages of both n-type and p-type transistors in a low-impurity channel transistor at a smaller number of steps. This ensures reduction in fabrication cost and enhancement in a fabrication yield.

Abstract: Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.

Abstract: A rear light entry photodetector array chip is secured face-down with solder on to the front face of a ceramic submount provided with electrically conductive vias. A frame-shaped mass of solder seals the chip to the submount to provide a hermetic enclosure protecting sensitive semiconductor surface areas of the photodetector chip array where electric fields are liable to be present in the vicinity of a pn or metal/semiconductor junction. The place of the photodetector array can be taken by a similar construction array of semiconductor light-emissive opto-electronic devices, such as VCSELs, or a mixed array including emitters and detectors.