Abstract: A magnetic tunneling effect device capable of displaying a so-called magnetic tunneling effect in stability, more specifically, a magnetic tunneling junction device in which a first magnetic metal layer and a second magnetic metal layer are connected together by ferromagnetic tunnel junction via an insulating layer and in which the conductance of the tunnel current is changed by the relative angle of magnetization of these magnetic metal layers. The ferromagnetic tunnel junction has a junction area of not larger than 1 10−9 m2. For reliably controlling the junction area of the ferromagnetic tunnel junction, the insulating layer is formed by a first insulating layer for ferromagnetic tunnel junction and a second insulating layer formed on the first insulating layer for controlling the junction area of the ferromagnetic tunnel junction.

Abstract: A semiconductor module has a plurality of power semiconductor devices mounted on a substrate, and a metal foil for wiring is mounted on the substrate so that an asymmetric unit arrangement of the semiconductor devices is formed. In the device, all of the units are arranged in the same direction on the substrate, and all of the units are electrically connected with electrode terminal feet, and the electrode terminal feet are electrically connected with linkage terminal foot. The electrode terminal feet are disposed with a certain interval.

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: A method of preparing a semiconductor wafer includes the step of forming first and second layers of a first material on opposing respective first and second faces of the semiconductor wafer. The second layer of the first material is then removed from the second face of the semiconductor wafer. More particularly, the first material can be polysilicon. Warping of the semiconductor wafer can thus be reduced.

Abstract: A low temperature buffer layer made of GaN is formed on a sapphire substrate and an n type layer is formed thereon. An active layer is made of an InGaN based compound semiconductor. A GaN based compound semiconductor layer including an n-type layer, an active layer serving as a light emitting layer, and a p type layer are laminated on the sapphire substrate. A current diffusion film which is formed on the p-type layer for supplying the light emitting layer with a uniform current is formed of an electrically conductive metal having a high reflectance factor for light. The light emitting diode element is mounted on a circuit board so that the output light of the light emitting layer is emitted from the side of the sapphire substrate. Reflected light which is reflected on the current diffusion film is also emitted from the sapphire substrate.

Abstract: A method and structure for blowing a fuse including removing an insulator above a fuse link and etching the fuse link.

Abstract: A nitride semiconductor structure includes: a substrate having a growth surface, a convex portion and a concave portion being formed on the growth surface; and a nitride semiconductor film grown on the growth surface. A cavity is formed between the nitride semiconductor film and the substrate in the concave portion.

Abstract: A nitride semiconductor light emitting device which uses as a light emitting layer an indium-containing group-III nitride semiconductor layer of a multi-phase structure composed of a main phase and sub-phases having different indium contents is characterized in that the sub-phases are mainly formed of crystal whose boundary with the main phase is surrounded by a strained layer.

Abstract: In a hetero-junction bipolar transistor, an undoped Al0.7Ga0.3As stopper layer 5 having good etching controllability is provided on a base layer 4, thereby forming a base without etching damage, this resulting in achievement of the desired base resistance with good repeatability.

Abstract: A surface mount semiconductor diode device (50) having first (51) and second (53) coplanar contacts comprises a semiconductor element (52) having a first surface electrically mounted on a first member (54) formed of conductive material, which first member (54) has an arm (58) extending in a direction away from the semiconductor element (52) to an end (60) which forms the first contact (51). A cup member (62) formed of conductive material comprises a wall (64) extending from a bottom portion (66) so as to form an opening (68) surrounded by the wall (64). The semiconductor element (52) and first member (54) are mounted within the opening (68) such that a second surface of the semiconductor element (52) is electrically coupled to the bottom portion (66) of the cup member (62) and the end of the arm (58) extends above a top surface (72) of the wall (64).

Abstract: A mounting technology that increases the cw operating temperature of intersubband lasers, without increasing the risk of hot spots near the facets and short circuits near the perimeter of the laser chip, is described.

Abstract: Silicon carbide power devices having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region of first conductivity type (e.g., N-type) and a trench therein at a first face thereof. A uniformly doped silicon carbide charge coupling region of second conductivity type (e.g., an in-situ doped epitaxial P-type region) is also provided in the trench. This charge coupling region forms a P-N rectifying junction with the drift region that extends along a sidewall of the trench. The drift region and charge coupling region are both uniformly doped at equivalent and relatively high net majority carrier doping concentrations (e.g., 1×1017 cm−3) so that both the drift region and charge coupling region can be depleted substantially uniformly when blocking reverse voltages.

Abstract: A semiconductor integrated circuit device having a ball grid array package includes a core material including a semiconductor chip and a sealing resin layer surrounding the chip and surface materials including a carrier base and a reinforcement in a sandwich structure for high stiffness against being and high reliability of connection to a printed wiring board even during heat cycling.

Abstract: The present invention provides a leadframe package formed by flip chip on leadframe technique. The chips are face to face attached on both sides of the leadframe surface. Another embodiment according to the present invention is that the chips are back to back attached on a leadframe. A chip with smaller size is stacked on a further chip with larger size. The smaller chip is connected to the leadframe by wire bonding. The present invention includes a first chip attached on the leadframe by using flip chip technology. The first chip has a plurality of conductive bump for electrically transferring signal to external. The tape has a plurality of openings or slots through the tape. Each opening exposes the terminal of the inner leads. Thus, a further chip can be set on the opposite major surface of the leadframe by means of the openings or slots. The second chip can be optionally face to face formed on the other side of the leadframe or back to back stacked on the first chip.

Abstract: A light emitting device includes a heterojunction having a p-type layer and an n-type layer. The n-electrode is electrically connected to the n-type layer while the p-electrode is electrically connected to the p-type layer. The p and n-electrodes are positioned to form a region having uniform light intensity.

Abstract: A method is shown for producing a PIN photodiode using a reduced number of masks wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the intrinsic layer. A second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate. A groove is etched from the second surface of the fabrication substrate through the intrinsic region to the first surface in order to isolate the photodiode.

Abstract: Positioning marks 15, 16 are formed at predetermined positions with respect to an active layer 11 buried in an LD chip body 10. In an Au metallized layer 12 for solder joining on the active layer 11, marks 17, 18 for measurement are precisely formed by the same mask with which the positioning marks 15, 16 are formed. The marks 17, 18 for measurement are arranged closer to the active layer 11 in comparison with the positioning marks 15, 16. Therefore, the distances between the active layer 11 and the marks 17, 18 for measurement can be respectively measured with high accuracy. In mounting of the LD chip to a substrate in a passive alignment technique, relative positions of the active layer and the positioning marks are measured in advance with high accuracy and the LD chip can be mounted to the substrate by correcting both the relative positions. Thus, the LD chip is positioned with high accuracy to be mounted to the substrate.

Abstract: A field effect transistor has an InGaAs channel layer and an InGaP electron donor layer on a GaAs substrate. A natural superlattice is formed in the crystal of the InGaP electron donor layer, and a gate finger is formed to run in the [−110] direction. A method of manufacturing this field effect transistor is also disclosed.

Abstract: An FET (Field Effect Transistor) includes a substrate. Sequentially formed on the substrate area buffer layer (200 nm thick) formed of a first sphalerite type semiconductor implemented by In0.52Al0.48, a carrier running layer (6 nm thick) formed of a second sphalerite type semiconductor implemented by In0.53Ga0.47As, an InAs carrier running layer (7 nm thick), an AlAs spacer layer (2 nm thick), a spacer layer (2 nm thick) formed of a third sphalerite type semiconductor implemented by In0.52Al0.48As, a carrier supply layer (20 nm thick) formed of a fourth sphalerite type semiconductor implemented by n−In0.52Al0.48As with 3×1018 cm−3 of Si added thereto, a Schottky layer (15 nm thick) formed of a fifth sphalerite type semiconductor implemented by In0.52Al0.48As, and a cap layer (20 nm thick) formed of a sixth sphalerite type semiconductor implemented by n-In0.53Ga0.47As with 1×1019 cm−3 of Si added thereto.

Abstract: A semiconductor photonic device contains a substrate; a ZnO buffer layer provided on the substrate; and a semiconductor compound provided on the ZnO buffer layer and represented by InxGayAlzN wherein x+y+z=1, 0≦x≦1, 0≦y≦1 and 0≦z≦1, wherein the ZnO buffer layer has a lattice constant of about 5.2070 Å or more in the c-axis direction.