Abstract: Bipolar and field effect molecular wire transistors are provided. The molecular wire transistor comprises a pair of crossed wires, with at least one of the wires comprising a doped semiconductor material. The pair of crossed wires forms a junction where one wire crosses another, one wire being provided with Lewis acid functional groups and the other wire being provided with Lewis base functional groups. If both wires are doped semiconductor, such as silicon, one is P-doped and the other is N-doped. One wire of a given doping comprises the emitter and collector portions and the other wire comprises the base portion, which is formed by modulation doping on the wire containing the emitter and collector at the junction where the wires cross and between the emitter and collector portions, thereby forming a bipolar transistor. Both NPN and PNP bipolar transistors may be formed.

Abstract: A sensing element is formed on a silicon (Si) substrate and covered with a cap. The cap has a leg portion having a titanium layer and a gold layer formed in that order on the lower surface thereof. The silicon substrate has an Si bonding frame at a position corresponding to the leg portion. When bonding the Si bonding frame of the silicon substrate and the leg portion of the cap, the titanium layer deoxidizes a naturally oxidized silicon layer formed on the Si bonding frame, whereby the silicon substrate and the cap can be uniformly bonded together with an Au/Si eutectic portion interposed therebetween. In this case, the Au/Si eutectic portion includes a titanium oxide accompanying the deoxidization of the naturally oxidized silicon layer.

Abstract: A method is shown for producing a distributed PN photodiode having a first active region of the photodiode that can be made arbitrarily thin. A fabrication substrate is doped to have a first conductivity type in order to form the first active region of the photodiode. A layer can also be formed upon the first surface of the fabrication substrate or a first surface of a handling wafer, where the layer can be an oxide layer, where a thickness of the oxide layer can be controlled to form a dielectric refractive reflector, a reflective layer, or a conductive layer. The first surface of the handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the first active region. A plurality of second active regions of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate.

Abstract: A device forming a high energy resolution integrated semiconductor &Dgr;E-E detector telescope is disclosed, in which is formed a very thin &Dgr;E detector portion (14) primarily fabricated from a first semiconductor wafer which is bonded/silicidized to a second semiconductor wafer forming an E detector portion (18). This &Dgr;E-E detector provides a well supported very thin &Dgr;E detector for high resolution. The very thin &Dgr;E detector portion bonded/silicidized to the E detector portion further provides between each other a buried metallic layer (16) acting as a contact common to the two detectors, which metal layer is thin and presents a low resistivity.

Abstract: A method and apparatus for repair of a multi-chip module, such as a memory module, is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

Abstract: A cryogenic, high-resolution X-ray detector with high count rate capability has been invented. The new X-ray detector is based on superconducting tunnel junctions (STJs), and operates without thermal stabilization at or below 500 mK. The X-ray detector exhibits good resolution (˜5-20 eV FWHM) for soft X-rays in the keV region, and is capable of counting at count rates of more than 20,000 counts per second (cps). Simple, FET-based charge amplifiers, current amplifiers, or conventional spectroscopy shaping amplifiers can provide the electronic readout of this X-ray detector.

Abstract: Naturally occurring polarization-induced electric fields in a semiconductor light emitter with crystal layers grown along a polar direction are reduced, canceled or reversed to improve the emitter's operating efficiency and carrier confinement. This is accomplished by reducing differences in the material compositions of adjacent crystal layers, grading one or more layers to generate space charges and quasi-fields that oppose polarization-induced charges, incorporating various impurities into the semiconductor that ionize into a charge state opposite to the polarization induced charges, inverting the sequence of charged atomic layers, inverting the growth sequence of n- and p-type layers in the device, employing a multilayer emission system instead of a uniform active region and/or changing the in-plane lattice constant of the material.

Abstract: A lead frame assembly including at least two layers. A first of the lead frame layers includes a first wide, electrically conductive bus and a plurality of leads that extend substantially unidirectionally from a single edge of the lead frame assembly. The second lead frame layer includes a second wide, electrically conductive bus that is superimposed over the first bus and a plurality of lead fingers extending substantially unidirectionally from a single edge of the lead frame assembly. Preferably, the lead fingers of both the first and second layers extend in substantially the same direction. An insulator element is disposed between the first and second buses. One of the buses is connectable to a power supply source (Vcc), while the other is connectable to a power supply ground (Vss). Thus, the co-extensive portions of the first and second buses form a decoupling capacitor.

Abstract: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges. The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate.

Abstract: A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.

Abstract: The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a channel region; a pair of spaced conductively doped semiconductive regions in electrical connection with the channel region of the semiconductive layer; a gate intermediate the semiconductive regions; and a gate dielectric layer intermediate the semiconductive layer and the gate, the gate dielectric layer being configured to align the gate with the channel region of the semiconductive layer. In one aspect, chemical-mechanical polishing self-aligns the gate with the channel region. According to another aspect, a field emission device, includes a transistor configured to control the emission of electrons from an emitter.

Abstract: A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers.

Abstract: An epitaxial material grown laterally in a trench allows for the fabrication of a trench-based semiconductor material that is substantially low in dislocation density. Initiating the growth from a sidewall of a trench minimizes the density of dislocations present in the lattice growth template, which minimizes the dislocation density in the regrown material. Also, by allowing the regrowth to fill and overflow the trench, the low dislocation density material can cover the entire surface of the substrate upon which the low dislocation density material is grown. Furthermore, with successive iterations of the trench growth procedure, higher quality material can be obtained. Devices that require a stable, high quality epitaxial material can then be fabricated from the low dislocation density material.

Abstract: Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (810) is sensed by sensors (820) that output electrical signals in response to the analyte. The electrical signals may be preprocessed (830) by filtering and amplification. In one embodiment, a plurality of sensors are formed on a single integrated circuit. The sensors may have diverse compositions.

Abstract: A component has an active layer, barrier layers and, if appropriate, a buffer layer and at least one of these layers contains a beryllium-containing chalcogenide. The active layer is a multiple layer, for example a superlattice made of BeTe/ZnSe or of BeTe/ZnCdSe. When using an active layer of ZnSe on a substrate of GaAs, matching with low electrical resistance is achieved between the III-V materials and the II-VI materials by means of a pseudo-graded buffer layer including a beryllium-containing chalcogenide.

Abstract: A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

Abstract: Airbridge structures and processes for making air bridge structures and integrated circuits are disclosed. One airbridge structure has metal conductors 24 encased in a sheath of dielectric material 249. The conductors extend across a cavity 244 and a semiconductor substrate 238. In one embodiment, the conductors traversing the cavity 244 are supported by posts 248 that extend from the substrate. In another embodiment, oxide posts 258 extend from the substrate to support the conductors. In another embodiment, trenches 101 are made in a device substrate 110 bonded to a handle substrate 100. The trenches are filled with a dielectric and a conductor pattern is formed over the filled trenches. The substrate material between the conductors is then removed to leave a pattern of posts 116, 114, 112 that included dielectrically encased conductors 106. In another bonded wafer embodiment, conductors 204 are encased in a dielectric above a sacrificial device region.

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

Abstract: An electron flux amplifier is provided wherein a microchannel plate (MCP) is monolithically formed with, or bonded to, a semiconductor amplifier. In a preferred embodiment, microchannels are formed to extend into a semiconductor substrate to a predetermined depth from the surface, and a collection diode is formed in the substrate beneath the channels. The collection diode may comprise a single planar diode, or a plurality of electrically isolated diodes to provide for imaging of the electron flux. The electron flux amplifier may be used as a detector in a photomultiplier tube (PMT) having a photoelectronically responsive input surface and one or more accelerating electrodes for directing a photoelectron flux toward the electron flux amplifier.

Abstract: A semiconductor structure and a scheme for forming a layer of amorphous material on a semiconductor substrate are provided. In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising an amorphous alloy formed over at least a portion of a semiconductor substrate. The amorphous alloy comprises amorphous aluminum nitride (AlN) and amorphous gallium nitride (GaN). The amorphous alloy may be characterized by the following formula: AlxGa1−xN where x is a value greater than zero and less than one. The amorphous alloy may further comprise indium nitride. Relative proportions of aluminum and gallium in the amorphous aluminum gallium nitride alloy are controlled to engineer the band gap of the amorphous alloy.