Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.

Abstract: A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell.

Abstract: Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a fuse protection diode, a fuse programming transistor, and a fuse cell electrically connected in series between a first pad and a second pad. The fuse system further includes a bias generator that biases a gate of the fuse programming transistor to control an amount of current provided to the fuse cell. The fuse protection diode helps prevent inadvertent programming of the fuse cell by blocking current from flowing through the fuse cell in response to a decrease in voltage of the first pad relative to the second pad.

Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.

Abstract: An operating method of a memory device is provided. Using a statistical model, a resistance Rdyn of a variable resistor of a memory cell and a variation ?Rdyn of the resistance Rdyn are determined. Based on the resistance Rdyn and the variation ?Rdyn of the resistance Rdyn, an average resistance Rdyn_avg and a beta value of the variable resistor are determined. Then, using the average resistance Rdyn_avg and the beta value, a resistance Ra of an insertion resistor, connected between the memory cell and a power supply generator for generating a power supply voltage VPGM, is determined.

Abstract: Various examples are provided examples related to resistive content addressable memory (RCAM) based in-memory computation architectures. In one example, a system includes a content addressable memory (CAM) including an array of cells having a memristor based crossbar and an interconnection switch matrix having a gateless memristor array, which is coupled to an output of the CAM. In another example, a method, includes comparing activated bit values stored a key register with corresponding bit values in a row of a CAM, setting a tag bit value to indicate that the activated bit values match the corresponding bit values, and writing masked key bit values to corresponding bit locations in the row of the CAM based on the tag bit value.

Abstract: A computer-implemented method of designing a dental restoration at a display includes providing a virtual three dimensional representation of at least a portion of the patient's dental situation. The method includes displaying a library arch form in an alignment with the virtual three dimensional representation of the portion of the patient's dentition. The library arch form includes a pair of two virtual library teeth packing to each other. The method also includes in response to a parametric change of one of the two virtual library teeth, moving the other virtual library tooth to keep packing to the changed virtual library tooth.

Abstract: A nonvolatile memory device includes a target memory area; a control unit configured to apply a program pulse one or more times to the target memory area in response to a program command, until program verification passes; and a status storage unit configured to store a program status information for the target memory area, wherein the control unit is supplied with a first operation voltage, and the status storage unit is supplied with a second operation voltage.

Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

Abstract: A driving assistance apparatus includes: an estimation unit configured to estimate a brake-on vehicle speed as a vehicle speed at which a driver of a vehicle starts a brake operation, based on information related to deceleration of the vehicle and vehicle-speed information; a deceleration-operation-point calculation unit configured to calculate location information of a deceleration-operation point where the driver of the vehicle starts a deceleration operation, based on the brake-on vehicle speed; and an information presentation unit configured to present driving assistance information for prompting the driver of the vehicle to perform the deceleration operation, corresponding to the calculated location information of the deceleration-operation point and a running position of the vehicle.

Abstract: A semiconductor memory device which is capable of high-speed operation in synchronization with external control signals is provided. The semiconductor memory device has a data input portion, a memory array, a data output portion, and a control portion. The data input portion receives command and address input data in response to the external control signals. The memory array has a plurality of memory elements. The data output portion outputs data read from the memory array in response to the external control signals. The control portion has the function of delay-compensation. During the time interval for receiving the input data, the function of delay-compensation estimates the delay time of the internal circuits, stores the estimated delay-time in a memory unit, and adjusts the output timing of the data output portion.

Abstract: A memory device includes a plurality of memory cells, a plurality of word lines, and a word line driver. The word lines are respectively coupled to the memory cells. The word line driver is configured to respectively drive the word lines with word line signals that have varying pulse widths.

Abstract: A memory system includes a first flash memory, a second flash memory and a controller. The first flash memory includes a memory array divided into a plurality of pages. The controller is coupled to the first flash memory and the second flash memory and configured to: control the second flash memory to record an address of a particular page in the first flash memory before programming the particular page; and control the second flash memory to record a program status of the particular page after the particular page has been programed.

Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device also utilizes a plurality of orthogonal spin transfer magnetic tunnel junction (OST-MTJ) stacks connected in series, with each OST-MTJ stack capable of selective activation by application of an external magnetic field, thereby allowing efficient writing of the bit without a concomitant increase in read disturb.

Abstract: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.

Abstract: A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip). The first semiconductor chip includes a plurality of temperature sensors disposed in mutually different places, and a memory controller that controls each of a plurality of memory areas provided in the second semiconductor chip based on output results of a respective one of the plurality of temperature sensors.

Abstract: A last written page in an open block in NAND flash is identified where the NAND flash includes a plurality of pages and the last written page has first content. Second content is written to an adjacent page in the open block, wherein the adjacent page is physically adjacent to the last written page in the open block and the second content enhances robustness of the first content.

Abstract: An integrated circuit device includes a first memory cell that stores data representative of configuration data when operating in a first mode, wherein the first memory cell stores data representative of user-accessible data when operating in a second mode. The integrated circuit device also includes a second memory cell that stores a value indicating whether the first memory cell is operating in the first mode or is operating in the second mode. The integrated circuit device further includes a switch coupled to the first memory cell and controlled by the second memory cell, wherein the switch provides a defined value to be read in place of the stored data of the first memory cell when the second memory cell stores the value indicating that the first memory cell is operating in the second mode.

Abstract: A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.