Abstract: A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.

Abstract: Disclosed are a high voltage switch circuit and a semiconductor memory device including the same. The high voltage switching circuit includes: a control signal generating circuit configured to supply a supply voltage to an internal node and generate a control signal in response to a first enable signal; a well bias generating circuit configured to apply a well bias to a well of a transistor included in the control signal generating circuit in response to a second enable signal; and a switching circuit configured to switch an input voltage to an output voltage in response to the control signal.

Abstract: A data storage device includes a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of SLC-data blocks, a plurality of TLC-spare blocks and a plurality of TLC-data blocks. The controller writes data into the SLC-spare blocks in response to a write command arranged to write the data into the flash memory, wherein when a first predetermined condition is satisfied, the controller selects a plurality of first TLC-data blocks with the least amount of valid data from the TLC-data blocks, writes valid data stored in the first TLC-data blocks into at least one first TLC-spare block, and releases the TLC-data blocks to increase the number of TLC-spare blocks by one.

Abstract: A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.

Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.

Abstract: An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies. Each memory die may have a size less than a total size of the memory and include a plurality of cells. The memory may perform a program operation to write to and verify one or more of the plurality of cells in response to receiving a program command. The controller may be configured to issue the program command to program the plurality of memory dies and to issue the polling status command after issuing the program command to obtain a number of the cells that failed to be verified during the program operation. In response to the polling status command received from the controller, the memory reports a count of a number of bit-lines not having an inhibited state in the write buffer.

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

Abstract: Memories include first and second arrays of non-volatile memory cells, a first plurality of data lines containing a first number of data lines selectively connected to respective subsets of the first array of non-volatile memory cells, a second plurality of data lines containing a second number of data lines, less than the first number, selectively connected to respective subsets of the second array of non-volatile memory cells, and sense circuitry selectively connected to the first and second pluralities of data lines. The memories are configured, when reading the second array of non-volatile memory cells, to connect the sense circuitry to each data line of the second plurality of data lines, and the memories are configured, when reading the first array of non-volatile memory cells, to connect the sense circuitry to a number of data lines of the first plurality of data lines equal to the second number.

Abstract: An apparatus for estimating a state of a secondary battery by using an Extended Kalman Filter is provided, in which the secondary battery includes a positive electrode including a first positive electrode material and a second positive electrode material having different operating voltage ranges from each other, a negative electrode including a negative electrode material, and a separator interposed therebetween.

Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.

Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

Abstract: A programmable non-volatile memory device effectuates two different functions (read, erase (re-program)) during a single instruction or command. During a first phase of the command a cell state is determined by a memory controller circuit, and in a second phase of the same command the cell state is re-written. This implementation is useful for applications where it is desirable to permit one time access only of particular data/content.

Abstract: An address decoder, for a non-volatile memory device provided with a memory array having memory cells arranged in word lines (WL) and bit lines (BL), each memory cell being having a memory element and an access element with a MOS transistor for enabling access to the memory element. Source terminals of the MOS transistors of the access elements of the memory cells of a same word line are connected to a respective source line. The address decoder has a row-decoder circuit and a column-decoder circuit, for selecting and biasing the word lines and the bit lines, respectively, of the memory array with row-driving signals (VWL) and column-driving signals (VBL), respectively. The address decoder has a source-decoder circuit for generating source-driving signals (VSL) for biasing the source lines of the memory array, on the basis of the logic combination of the row-driving signals of associated word lines.

Abstract: The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Abstract: An apparatus for estimating state of a hybrid secondary battery including a first secondary battery and a second secondary battery having different electrochemical characteristics from each other and being connected in parallel with each other, is provided.

Abstract: A SRAM memory bit cell is provided that includes a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); and a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains). The control circuit is configured to provide, during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p TFET. The control circuit is further configured to provide, during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.

Abstract: An object is to provide a memory element having a novel structure where data can be held even after power supply is stopped. The memory element includes a latch circuit, a first selection circuit, a second selection circuit, a first nonvolatile memory circuit, and a second nonvolatile memory circuit. The first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor and a capacitor. The transistor included in each of the first nonvolatile memory circuit and the second nonvolatile memory circuit is a transistor in which a channel is formed in an oxide semiconductor film. The off-state current of such a transistor is extremely small. The transistor is turned off after data is input to a node where the transistor and the capacitor are connected to each other, and data can be held for a long time even after supply of power supply voltage is stopped.