Patents Examined by Douglas King
  • SRAM with stacked bit cells
    Patent number: 10453522
    Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semicoductor Manufacturing Co., Ltd.
    Inventors: Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge, Ta-Pen Guo
  • Automatic calibration (autocal) error recovery for a memory sub-system
    Patent number: 10446241
    Abstract: Several embodiments of memory devices and systems with walking read level calibration are disclosed herein. In one embodiment, a system includes a memory component having at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to perform iterative calibrations of the memory region by determining a first read level offset value during a first calibration. A new base read level test signal is determined based on the first read level offset value. During a second calibration using the new base read level test signal, a second read level offset value is determined.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni
  • Memory system and method of operating the same
    Patent number: 10445021
    Abstract: Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 15, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwang Su Kim
  • Hybrid memory system and method of operating the same
    Patent number: 10437499
    Abstract: The present disclosure provides a hybrid memory system and a method of operating the same. The hybrid memory system includes a non-volatile memory, a volatile memory and a controller. The volatile memory stores data. The controller is configured to move the data from the volatile memory to the non-volatile memory in response to a command to enter a power-saving mode. The controller precludes the volatile memory from having a self-refresh operation performed thereon after the movement of the data.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 8, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Boosted channel programming of memory
    Patent number: 10431310
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Circuit and method for storing information in non-volatile memory during a loss of power event
    Patent number: 10430296
    Abstract: A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Juan Manuel Cesaretti, Alejandro Gabriel Milesi
  • Magnetic element and magnetic memory
    Patent number: 10424724
    Abstract: According to one embodiment, a magnetic element includes a first member and a first magnetic portion. The first member includes a first region, a second region, and a third region positioned between the first region and the second region in a first direction. The first region includes at least one first element selected from the group consisting of Au, Ir, Al, Ta, TaN, W, Hf, Pt, and Pd. The second region includes at least one second element selected from the group. The third region includes at least one third element selected from the group. A concentration of the third element in the third region is lower than a concentration of the first element in the first region and lower than a concentration of the second element in the second region. A direction from the first region toward the first magnetic portion is aligned with a second direction.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: September 24, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Nobuyuki Umetsu, Tsuyoshi Kondo, Yasuaki Ootera, Takuya Shimada, Michael Arnaud Quinsat, Masaki Kado, Susumu Hashimoto, Shiho Nakamura
  • Non-volatile memories and data reading methods thereof
    Patent number: 10410727
    Abstract: A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and second bit line decoders, a comparator circuit including a first input terminal and a second input terminal, and a bias generation circuit generating a bias voltage. When reading a data information from a first memory cell, a first output voltage of the first memory cell is sent to the first input terminal and the bias voltage is sent to the second input terminal. When reading a data information from a second memory cell, a second output voltage of the second memory cell is sent to the second input terminal and the bias voltage is sent to the first input terminal.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: September 10, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yi Jin Kwon, Hao Ni, Jim Chia-Ming Hsu, Xiao Yan Liu
  • Systems and methods for writing zeros to a memory array
    Patent number: 10402116
    Abstract: A memory device may include a memory array that includes multiple memory cells. The memory device may also include multiple sense amplifiers that, in operation, may each be connected to one or more memory cells. The sense amplifiers may be designed to assist in writing logical zeros to the multiple memory cells.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Byung S. Moon, Harish N. Venkata, Gary L. Howe, Myung Ho Bae
  • Semiconductor devices
    Patent number: 10403334
    Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Byung Kuk Yoon, Honggyeom Kim
  • Memory device and memory system including the same
    Patent number: 10403332
    Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Geun Lee, Young Jin Cho, Hee Hyun Nam, Hyo Deok Shin, Young Kwang Yoo
  • Techniques for precharging a memory cell
    Patent number: 10403336
    Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Umberto Di Vincenzo
  • Flash memory block retirement policy
    Patent number: 10387281
    Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Thomson
  • Storage device, host communicating with the storage device, and electronic device including the storage device
    Patent number: 10387064
    Abstract: A storage device includes a connector including a plurality of connection terminals connectable to an external device and a nonvolatile memory including a secure area and a normal area. The secure area is accessible when the secure signal indicates the secure mode, and the normal area is accessible when the secure signal indicates the non-secure mode. One of the plurality of connection terminals corresponds to a secure signal terminal for receiving a secure signal that indicates a secure mode or a non-secure mode.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-Soo Kim
  • Memory cell selector and method of operating memory cell
    Patent number: 10388371
    Abstract: Embodiments provide a selector device for selecting a memory cell. The selector device includes a first electrode; a second electrode; and a switching layer sandwiched between the first electrode and the second electrode. The switching layer includes at least one metal rich layer and at least one chalcogenide rich layer. The metal rich layer includes at least one of a metal or a metal compound, wherein metal content of the metal rich layer is greater than 50 at. %. The chalcogenide content of the chalcogenide rich layer is greater than 50 at. %.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: August 20, 2019
    Assignee: Agency for Science, Technology and Research
    Inventors: Hongxin Yang, Minghua Li, Wei He, Yu Jiang, Fei Li
  • Integrated circuits including magnetic random access memory structures having reduced switching energy barriers for dual bit operation and methods for fabricating the same
    Patent number: 10381406
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have magnetizations independent of each other.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: August 13, 2019
    Assignee: Globalfoundries, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Integrated circuit
    Patent number: 10381070
    Abstract: An integrated circuit includes a plurality of first memory cells and a plurality of second memory cells. Each cell of the plurality of first memory cells includes a first inverter, a second inverter, a first pass-gate (PG) transistor and a second PG transistor. Each inverter of the first and second inverters includes a P-type single FinFET transistor and an N-type single FinFET transistor. The first PG transistor and the second PG transistor each are an N-type single FinFET transistor. Each cell of the plurality of second memory cells includes a third inverter, a fourth inverter, a third PG transistor and a fourth PG transistor. Each inverter of the third and fourth inverters includes a P-type single FinFET transistor and an N-type transistor. Each transistor of the third and fourth PG transistors include at least two FinFET transistors electrically coupled in a parallel configuration.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 13, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Apparatuses and methods for refreshing memory of a semiconductor device
    Patent number: 10381064
    Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Masaru Morohashi
  • Semiconductor memory device and method of operating the same
    Patent number: 10373689
    Abstract: Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform an erase operation on a selected memory block. The control circuit may control the peripheral circuit such that, during the erase operation, when the selected memory block has passed an erase verification, an additional erase verification operation is performed on memory cells coupled to a reference word line among a plurality of word lines coupled to the selected memory block, and the erase operation is performed according to a result of the additional erase verification operation for the memory cells coupled to the reference word line.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventor: Dong Hun Lee
  • Nonvolatile memory device
    Patent number: 10366750
    Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: July 30, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Norio Hattori, Masaru Yano