Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: A flexible display panel, a manufacturing method thereof, and a display device are provided. The flexible display panel includes a first base layer, a stress relief layer, a second base layer, and at least one adhesion enhancing layer. The first base layer, the stress relief layer, and the second base layer are sequentially stacked along a light exiting direction of the flexible display panel. The at least one adhesion enhancing layer is provided between the stress relief layer and at least one of the first base layer or the second base layer in such a manner that the adhesion enhancing layer enhances adhesion there between.

Abstract: A method for fabricating a neutron detector includes providing an epilayer wafer of Boron-10 enriched hexagonal boron nitride (h-10BN or h-BN or 10BN or BN) having a thickness (t), dicing or cutting the epilayer wafer into one or more BN strips having a width (W) and a length (L), and depositing a first metal contact on a first surface of at least one of the BN strip and a second metal contact on a second surface of the at least one BN strip. The neutron detector includes an electrically insulating submount, a BN epilayer of Boron-10 enriched hexagonal boron nitride (h-10BN or h-BN or 10BN or BN) placed on the insulating submount, a first metal contact deposited on a first surface of the BN epilayer, and a second metal contact deposited on a second surface of the BN epilayer.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor fin over a substrate, and a gate structure along sidewalls and the top surface of the semiconductor fin. The gate structure covers the first portion of the semiconductor fin. The semiconductor device also includes a source/drain feature adjacent to the gate structure. The semiconductor device further includes a source/drain contact connected to the source/drain feature. The source/drain contact extends downwards to a position that is lower than the top surface of the first portion of the semiconductor fin.

Abstract: A method of producing a quantum dot comprising zinc selenide, the method comprising: providing an organic ligand mixture comprising a carboxylic acid compound, a primary amine compound, a secondary amide compound represented by Chemical Formula 1, and a first organic solvent: RCONHR??Chemical Formula 1 wherein each R is as defined herein; heating the organic ligand mixture in an inert atmosphere at a first temperature to obtain a heated organic ligand mixture; adding a zinc precursor, a selenium precursor, and optionally a tellurium precursor to the heated organic ligand mixture to obtain a reaction mixture, wherein the zinc precursor does not comprise oxygen; and heating the reaction mixture at a first reaction temperature to synthesize a first semiconductor nanocrystal particle.

Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.

Abstract: A display apparatus comprises: a display panel to control emission or transmission of light to display an image; a support comprising a surface on which the display panel is placed; and a holding member that is adhered onto the surface of the support and engages with an edge of the display panel to hold the display panel at a given position of the surface, wherein the display panel has an opposite surface of a display surface of the display panel, the opposite surface being directed to the support; the holding member comprises a front surface portion formed using a light-transmitting material to cover the display surface, the front surface portion being plate shaped, and a frame portion comprising a rod-shaped member provided in such a manner as to be protruded from a first surface of the front surface portion and to be along an edge of the front surface portion, the first surface being directed to the display surface; and the front surface portion comprises a first functional layer on the first surface or on

Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

Abstract: In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.

Abstract: Disclosed are a flexible substrate, a preparation method thereof, and a display device, to improve the encapsulation effect and the product yield. The flexible substrate includes: a base substrate, where the base substrate has a plurality of sub-pixel areas arranged in an array, connection areas each for connecting adjacent sub-pixel areas; and hollow areas among the sub-pixel areas and the connection area; in each sub-pixel area, there are a pixel circuit, an isolation structure surrounding the pixel circuit, and a light-emitting functional layer covering the pixel circuit and the isolation structure; the isolation structure has a hollow pattern at a junction of the sub-pixel area and the connection area; the connection area has a signal line therein, and the signal line is electrically connected with the pixel circuit through the hollow pattern; and the isolation structure has an undercut that interrupts the light-emitting functional layer.

Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.

Abstract: A display panel includes a plurality of array sites arranged in an array defined by a plurality of rows and a plurality of columns. The display panel includes a first area of the array having a first pixel density and a second area of the array having a second pixel density lower than the first pixel density. The second area of the array includes a plurality of the array sites that are devoid of pixels. Rows of the second area that border the first area include at least one pixel and columns of the second area that border the first area include at least one pixel.

Abstract: The present disclosure discloses an array substrate with a display area, a manufacturing method thereof, a display panel, and a display device. The array substrate with the display area includes a base substrate, and a thin film transistor structure on a surface of the base substrate. The thin film transistor structure is in the display area, the thin film transistor structure includes at least a source-drain pattern and a planarization pattern. The source-drain pattern and the planarization pattern are on a side of the thin film transistor structure away from the base substrate. A surface of the planarization pattern away from the base substrate and a surface of the source-drain pattern away from the base substrate are substantially in a same plane, the planarization pattern has a first slot, and the source-drain pattern is accommodated in the first slot.

Abstract: Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

Abstract: A method (of generating a layout diagram) includes: generating one or more first conductive patterns representing corresponding conductive material in the first metallization layer, long axes of the first conductive patterns extending substantially in a first direction; generating a first deep via pattern representing corresponding conductive material in each of the second via layer, the first metallization layer, and the first via layer; relative to the first direction and a second direction substantially perpendicular to the first direction, aligning the first deep via pattern to overlap a corresponding component pattern representing conductive material included in an electrical path of a terminal of a corresponding transistor in the transistor layer; and configuring a size of the first deep via pattern in the first direction to be substantially less than a permissible minimum length of a conductive pattern in the first metallization layer.

Abstract: A display panel is provided. The display panel includes: a substrate having a display region and a bending region; a buffer layer having a first buffer layer disposed in the display region and a second buffer layer disposed in the bending region; a thin-film transistor disposed on the first buffer layer; an insulated combination layer disposed in the second buffer layer, a via hole is provided in the insulated combination layer and the second buffer layer; and a planarization layer disposed on the thin-film transistor and the insulated combination layer, and the planarization layer fills the via hole. A manufacturing method for a display panel is also disclosed. The present invention adopts an organic flat layer to fill the via hole, which can simplify the process flow and reduce the production cost while ensuring the flexibility of the bending region.

Abstract: Embodiments of the present disclosure provide an array substrate, a display device, a method for manufacturing an array substrate, a method for manufacturing a display device, and a spliced display device. The array substrate includes: a base substrate in which a through hole is provided; a filling portion disposed in the through hole, including a recessed structure and made from a flexible material; an electrically conductive pattern disposed on the filling portion and at least partially located in the recessed structure; and a film layer disposed on a side of the electrically conductive pattern facing away from the base substrate.

Abstract: Disclosed herein are integrated circuit devices and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.

Abstract: A substrate is capable of effectively reinforcing a connecting portion between an electronic component and the substrate. The substrate is a substrate on which a first electronic component having a plurality of bumps is to be mounted, and includes a base portion including an insulator and having, on the upper face thereof, at least one groove portion configured to store a tip portion of at least one of the bumps, and includes an electrode formed on at least the bottom face of the groove portion.