Abstract: A semiconductor device includes an electrode having a flat part and a non-flat part made up of a concave part, a joint layer being made of a sintered body of metal crystal grains provided on the flat part and the non-flat part of the electrode, and a semiconductor element being joined to the electrode with the joint layer therebetween, wherein the joint layer has a first region sandwiched between the non-flat part and the semiconductor element and a second region sandwiched between the flat part and the semiconductor element, and either one of the first region and the second region having a larger film thickness has a filling rate of the metal crystal grains smaller than the other one of the first region and the second region having a smaller film thickness. The present invention enhances reliability of a joint layer made of a sintered body of metal crystal grains.

Abstract: A pixel driving circuit and a manufacturing method thereof according to the present application use a process to manufacture a metal layer that includes a first metal pattern, a first shading pattern, a second metal pattern, a second shading pattern, a third shading pattern, and a third metal pattern on a substrate, and form a first anode pattern and a second anode pattern on a passivation layer, to form a drain of a first transistor, a drain of a second transistor, and a drain of a third transistor.

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.

Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

Abstract: A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.

Abstract: An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Abstract: An automation system including sensors that detect threats within a secured area, a plurality of prospective events defined within a memory of the automation system, each event including at least a physical change in an environment of the secured area, a time of execution of the physical change and a corresponding actuator that causes the physical change, a processor of the automation system that periodically activates the corresponding actuator at the time of each of the plurality of events, a processor that monitors each of the plurality of sensors for activation by an authorized human user and that saves a record of each activation to a cloud memory and a cloud processor that monitors the saved activation records of each sensor over a time period, determines a difference between the saved activations and the plurality of events and that modifies the plurality of events based upon the determined differences.

Abstract: A display panel and a display device are provided. The display panel includes first display region and second display region at least partially surrounding the first display region. A density of the pixel units in the first display region is smaller than in the second display region. In the first display region, along a row direction, the first pixel unit in the first pixel unit row is between two adjacent second pixel units in the second pixel unit row, and the second pixel unit in the second pixel unit row is between two adjacent first pixel units in the first pixel unit row. The first pixel circuit and the second pixel circuit are connected to a same first or second signal line. The first pixel unit connected to the first pixel circuit and the second pixel unit connected to the second pixel circuit are located in adjacent rows or columns.

Abstract: A display panel has a ratio y1 of an aperture ratio of the red pixel to an aperture ratio of the green pixel being in the range of 0.78e{circumflex over (?)}(?1.98r)?y1?2.297{circumflex over (?)}(?1.85r), and 0.1?y1?3, where r is a ratio of a luminous efficiency of the red pixel to a luminous efficiency of the green pixel. A ratio y2 of an aperture ratio of the blue pixel to the aperture ratio of the green pixel is in a range of 1.32e{circumflex over (?)}(?10.7b)?y2?5.95e{circumflex over (?)}(?14.1b), and 0.3?y2?4, where b is a ratio of a luminous efficiency of the blue pixel to the luminous efficiency of the green pixel.

Abstract: A foldable display apparatus may include a first display panel and a component. The first display panel may include a first section and a second section. The first section may include a first pixel set and a first transmission structure surrounded by the first pixel set. The second section may include a second pixel set, may include a second transmission structure surrounded by the second pixel set, and may rotate relative to the first display section about a folding axis. A distance from the folding axis to a center of the first transmission structure may be substantially equal to a distance from the folding axis to a center of the second transmission structure. The component may overlap the first transmission structure. The second transmission structure may overlap the first transmission structure and the component when the foldable display apparatus is in a folded state.

Abstract: A surface mount (SMD) diode taking a runner as the body and a manufacturing method thereof are described. An elongated runner groove is adopted to cure and package groups of diode chips arranged side by side and corresponding copper pins thereon, with the utilization rate of epoxy resin up to 90% or more. The use cost of epoxy resin is thus reduced, and environmental pollution is also reduced.

Abstract: A display apparatus comprises: a display panel to control emission or transmission of light; a support comprising a surface on which the display panel is placed; and a holding member that is adhered onto the surface and engages with an edge of the display panel to hold the display panel at a given position of the surface. The holding member comprises a front surface portion formed using a light-transmitting material to cover a display surface of the display panel and a frame portion provided, on a first surface of the front surface portion, along an edge of the front surface portion. The first surface is directed to the display surface. The front surface portion comprises a first functional layer having a given function related to propagation of light on the first surface or on a second surface opposite the first surface.

Abstract: A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.

Abstract: A semiconductor device includes a compound semiconductor layer, an oxide layer over and contacting the compound semiconductor layer, a nitride layer over and contacting the oxide layer, and a dielectric layer over and contacting the nitride layer. At least a portion of the oxide layer comprises a first crystalline structure. At least a portion of the nitride layer comprises a second crystalline structure.

Abstract: An organic EL light-emitting element is provided in which, by means of an organic material that is a oligomer with a molecular weight of 300-5000, an organic layer coated film 25 is formed in a high-definition pixel pattern in the openings 23a of insulation banks 23 that are formed with a hydrophilic material; a manufacturing method of said organic EL light-emitting element is also provided. The coated film 25 is formed by dropwise injection of a liquid composition containing an organic material oligomer.

Abstract: A semiconductor device includes an internal circuit and a power mesh configured to transmit an operating voltage to the internal circuit. The power mesh includes first power lines extending in a first direction and arranged in a second direction intersecting with the first direction, when viewed from a top; second power lines sharing lanes with the first power lines and at least partially overlapping with the first power lines in the second direction; first power straps extending in the second direction and coupled to the first power lines; and second power straps extending in the second direction and coupled to the second power lines. Each of the first and second power lines may have a width of the same size as a width of each lane in sections where they do not overlap, and may have a width of a size smaller than the width of each lane in sections where they overlap.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first conductor layers stacked in a first direction, a second conductor layer provided above the first conductor layer, a first semiconductor layer extending in the first direction in the plurality of first conductor layers, a second semiconductor layer including a first portion extending in the first direction in the second conductor layer and a second portion of which a diameter in a cross section orthogonal to the first direction is larger than a diameter of the first portion, and being in contact with the first semiconductor layer in the second portion, and a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer. An upper end of the first charge storage layer protrudes upward in the first direction in comparison with an upper end of the first semiconductor layer.

Abstract: A light emitting module and the like having a higher heat-dissipation effect includes a light emitting element mounting substrate, one or more light emitting elements, a heatsink including a through-hole in a position corresponding to a screw hole, a bolt screwed in the screw hole and fastening the heatsink and a metal plate or a full thread and a nut for the fastening. In the light emitting element mounting substrate, the metal plate, an insulating layer, and an electrode layer on which the one or more light emitting elements are mountable are stacked in this order. The metal plate includes a bottomed screw hole opened at a surface opposite to a surface in contact with the insulating layer. The bolt or the full thread and the nut have a heat conductivity equal to or greater than that of the metal plate.

Abstract: An array substrate includes an electrostatic shielding layer disposed on a substrate, an isolating layer covering the electrostatic shielding layer, gate lines, data lines, and thin film transistors. The gate lines, the data lines, and the thin film transistors are disposed on the isolating layer. An orthographic projection of a pattern of the electrostatic shielding layer on the substrate covers an orthographic projection of at least one of a pattern of the gate lines, a pattern of the data lines, and a pattern of the thin film transistors on the substrate.

Abstract: Various methods and structures for fabricating a semiconductor structure. The semiconductor structure includes in a top layer of a semiconductor stack a semiconductor contact located according to a first horizontal pitch. A first metallization layer is disposed directly on the top layer and includes a metallization contact located according to a second horizontal pitch, the second horizontal pitch being different from the first horizontal pitch such that the location of the metallization contact is vertically mismatched from the location of the semiconductor contact. A second metallization layer is disposed directly on the first metallization layer. The second metallization layer includes a super viabar structure that forms an electrical interconnect, in the second metallization layer, between the semiconductor contact in the top layer of the semiconductor stack and the metallization contact in the first metallization layer.