Abstract: Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

Abstract: A display module and a method for manufacturing a display module, and a display device are provided. The display module includes a display panel, a main flexible printed circuit board, a secondary flexible printed circuit board and a driving circuit. The display panel comprises a signal line. The main flexible printed circuit board is at least partially on a first side of the display panel and is electrically connected to the signal line. The secondary flexible printed circuit board is at least partially on a second side of the display panel and is electrically connected to the signal line. The driving circuit is configured to provide signals to the signal line through the main flexible printed circuit board and the secondary flexible printed circuit board respectively.

Abstract: An organic light-emitting display apparatus includes a substrate having a display area displaying an image and a periphery area. The periphery area is located next to the display area. A first organic insulating layer is disposed on the substrate. The first organic insulating layer includes a valley portion separating the first organic insulating layer from the periphery area. A plurality of organic light-emitting devices is disposed on the substrate. Each of the organic light-emitting devices includes a first electrode, an emission layer, and a second electrode, sequentially disposed over the first organic insulating layer. The second electrode covers the emission layer and the valley portion. A second organic insulating layer is disposed over the first organic insulating layer and incudes a first opening exposing a center portion of the first electrode and a second opening overlapping the valley portion. A capping layer covers the second electrode.

Abstract: The embodiment of this application discloses a display panel, the display panel includes a first display area, a second display area, and a non-display area; the non-display area and the second display area are disposed adjacent to each other; the first display area surrounds the second display area and the non-display area; the first display area includes at least one first pixel unit; and the second display area includes at least one second pixel unit, wherein an area of the at least one second pixel unit is less than an area of the at least one first pixel unit.

Abstract: An integrated circuit includes a substrate and a first conductive line extending in a first direction parallel to a top surface of the substrate, wherein the first conductive line is a first distance from the top surface of the substrate. The integrated circuit further includes a second conductive line extending in a second direction parallel to the top surface of the substrate, wherein the second conductive line is a second distance from the top surface of the substrate, and the second distance is greater than the first distance. The integrated circuit further includes a third conductive line extending in the first direction, wherein the second conductive line is a third distance from the top surface of the substrate, and the third distance is greater than the second distance. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line.

Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

Abstract: A display apparatus includes a base substrate. A first data line is disposed on the base substrate. A first insulating layer is disposed on both the data line and the base substrate. An amorphous silicon conductive layer is disposed on the first insulating layer. A second insulating layer is disposed on the amorphous silicon conductive layer. A second data line is disposed on the second insulating layer.

Abstract: A semiconductor integrated circuit includes: a p?-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.

Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.

Abstract: The present disclosure discloses a color film assembly, a display substrate and a method for fabricating the same, and a display apparatus. The color film assembly includes a quantum dot layer, and a filter layer on a light emitting side of the quantum dot layer. The filter layer includes filter units. Each of the filter units includes a first filter structure. A light emitting surface of the first filter structure has at least one converging structure. The quantum dot layer includes quantum dot units which are in one-to-one correspondence with the filter units. Each quantum dot unit includes at least one quantum dot structure. The quantum dot structures in each quantum dot unit are in one-to-one correspondence with the first filter structures in the corresponding filter unit.

Abstract: A display substrate having a display area and a peripheral area is provided. The display substrate in the peripheral area includes a flexible base substrate; a first insulating layer on the flexible base substrate; a first signal line layer including a plurality of first signal lines on a side of the first insulating layer away from the flexible base substrate; and a second insulating layer on a side of the first signal line layer away from the flexible base substrate. The display substrate has a plurality of first vias extending through a respective one of the plurality of first signal lines, exposing a first surface of the first insulating layer; and the second insulating layer extends through the plurality of first vias to be in direct contact with the first surface of the first insulating layer.

Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

Abstract: Embodiments of the present disclosure provide an organic electroluminescent display panel, a display device, and a detection method.

Abstract: An organic light-emitting diode array substrate and manufacturing method thereof, and display apparatus are provided. The organic light-emitting diode array substrate includes: a base substrate; a first metal layer disposed on the base substrate; a first insulating layer disposed on a side of the first metal layer far away from the base substrate; a second metal layer disposed on a side of the first insulating layer far away from the base substrate; the first metal layer includes a first power line, and the second metal layer includes a second power line; the second power line is connected in parallel with the first power line through a first via hole which penetrates the first insulating layer.

Abstract: The present invention provides an organic light emitting diode (OLED) display panel and a manufacturing method of the OLED display panel. The present invention improves a light transmittance of an entire array layer by reducing the number of thin film transistors in an array layer under a camera-under-panel (CUP) region, and at the same time, patterning a cathode layer corresponding to a position of the CUP region to improve a light transmittance of the cathode layer, so that the CUP region can provide clear imaging, and the CUP region can also display images normally.

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

Abstract: Provided are an optical sensor including graphene quantum dots and an image sensor including an optical sensing layer. The optical sensor may include a graphene quantum dot layer that includes a plurality of first graphene quantum dots bonded to a first functional group and a plurality of second graphene quantum dots bonded to a second functional group that is different from the first functional group. An absorption wavelength band of the optical sensor may be adjusted based on types of functional groups bonded to the respective graphene quantum dots and/or sizes of the graphene quantum dots.

Abstract: A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.