Abstract: A subsystem logics partitioning and managing apparatus comprises a recognition unit for recognizing logical and physical resources that constitute a subsystem a partition definition table in which the logical and physical resources in the subsystem are assigned for each user at an interface level at which a storage configuration can be referenced by a storage management program an account table in which an account is set for each user-specific partition defined in the partition definition table a receiving unit for receiving a user account transmitted from an information processing unit and checking the received user account against the account table, to recognize a partition that corresponds to the user and a unit for outputting, at a GUI level, logical resources and physical resources that are contained in the recognized partition to an output interface as a resource configuration in the subsystem.

Abstract: Isolated memory is implemented by controlling changes to address translation maps. Control over the maps can be exercised in such a way that no virtual address referring to an isolated page is exposed to any untrusted process. Requests to edit an entry in a map are evaluated to ensure that the edit will not cause the map to point to isolated memory. Requests to change which map is active are evaluated to ensure that the map to be activated does not point to isolated memory. Preferably, these evaluations are performed by a trusted component in a trusted environment, since isolation of the memory depends on the evaluation component not being compromised. In systems that require all memory access requests to identify their target by virtual address, preventing the address translation maps from pointing to a portion of memory effectively prevents access to that portion of memory, thereby creating an isolated memory.

Abstract: Provided are a method, system, and program for establishing a point-in-time copy. Input/Output (I/O) requests to tracks identified as source tracks and corresponding target tracks in a point-in-time copy relationship are suspended until the point-in-time copy relationship is established. At least one data structure providing information on the source tracks and corresponding target tracks in the point-in-time copy relationship is generated, wherein the point-in-time copy relationship is established before data at the source tracks is copied to the target tracks and before source tracks in cache at the point-in-time are destaged to storage.

Abstract: Tables (FIGS. 11 and 12) for stipulating information (WWN: WorldWide Name) for primarily identifying computers, information (GID: Group ID) for identifying a group of the computers and a logical unit number (LUN) permitting access from the host computer inside storage subsystem, in accordance with arbitrary operation method by a user, and for giving them to host computer. The invention uses management table inside the storage subsystem and gives logical unit inside storage subsystem to host computer group arbitrarily grouped by a user in accordance with the desired form of operation of the user, can decide access approval/rejection to the logical unit inside the storage subsystem in the group unit and at the same time, can provide the security function capable of setting interface of connection in the group unit under single port of storage subsystem without changing existing processing, limitation and other functions of computer.

Abstract: A system for data backup includes a storage device, a backup storage device, and an intermediate storage device. Backup procedure is performed on-line and copies data blocks from the storage device into the backup storage device. When a write command is directed to a data storage block identified for backup that has not yet been backed up, the identified data storage block is copied from the storage device to the intermediate storage device, the write command is executed on the identified data storage block from the storage device, and the data storage block is copied from the intermediate storage device to the backup storage device. In case of an error accessing a block on the storage device, the block is marked as invalid. The intermediate storage device can be external to a file system of a computer that includes the storage device, or can be located in the storage device, or can be a separate partition of the storage device, or can be a file within a file system.

Abstract: A method is provided for controlling a cache system. The cache system to be controlled comprises a direct-mapped cache configured with a small block size, and a fully associative spatial buffer configured with a large block, which includes a plurality of small blocks. Where accesses to the direct-mapped cache and the fully associative buffer are misses, data of a missed address and data of adjacent addresses are copied to the large block in the fully associative spatial buffer according to a first-in-first-out (FIFO) process. Furthermore, if one or more small data blocks is accessed among its corresponding large block of data which is to be expelled from the fully associative buffer, the small block(s) accessed is copied to the direct-mapped cache.

Abstract: Systems and methods that provide a one-time programmable (OTP) memory with fault tolerance are provided. In one example, the OTM memory may include a data portion and a multistage programming (MSP) portion. The data of the data portion may be protected by error coding. The MSP portion may include at least one MSP bit and at least one respective redundant MSP bit.

Abstract: Provided are a method, system, and program for managing a relationship between one target volume and one source volume. Information is maintained in memory on an existing relationship between at least one source volume and at least one target volume, comprising: (i) at least one element, wherein each element represents a range of sequential data units in the volume; (ii) at least one relationship entry, wherein each relationship entry represents one relationship; and (iii) at least one element pointer associating one element with one relationship entry, wherein the data units represented by the element are part of the relationship represented by the relationship entry that the pointer associates with the element. A new relationship between at least one target volume and at least one source volume is added.

Abstract: Provided are a method, system, and program for managing a relationship between one target volume and one source volume. For each of the source volume and target volume, the memory includes: (i) at least one element, wherein each element represents a range of sequential data units in the volume; (ii) at least one relationship entry, wherein each relationship entry represents one relationship; (iii) at least one element pointer associating one element with one relationship entry, wherein the data units represented by the element are part of the relationship represented by the relationship entry that the pointer associates with the element; and (iv) one relationship pointer for each relationship entry associating the relationship entry with volume metadata, wherein the volume metadata provides information on the relationship represented by the relationship entry.

Abstract: A method of controlling access to a model specific register of a microprocessor. A method of controlling access to a model specific register of a processor having a normal execution mode and a secure execution mode may include storing processor state and mode information in the model specific register. Further, the method may include protection logic allowing a software invoked write access to modify the information within the model specific register during the normal execution mode. The method may further include security logic selectively inhibiting the software invoked write access during the secure execution mode.

Abstract: A data processing device for taking out necessary packet data from a sector in which a plurality of packet data exist in a mixed manner includes an audio decoder unit that has, in parallel, an audio packet extraction unit for extracting an audio packet made up of audio data with respect to an input of sector data from an external memory connected to a front-end processor unit, a supplementary packet extraction unit for extracting a supplementary packet made up of supplementary data, and a frame information extraction unit. Thus, when collectively providing the front-end processor unit and the audio decoder unit on one chip, a buffer memory for the frame state can be omitted.

Abstract: A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.

Abstract: In accordance with one aspect of the present invention, a seek profile table used by a disk controller contains multiple profiles for seek operations, and is accessed by a separate index table containing, for each permutation of key parameters, an index to a corresponding profile. In operation, the estimated seek time for an enqueued data access operation is obtained by accessing the applicable index table entry, using the value of the index entry to determine the corresponding profile, and using the profile to estimate the access time. Preferably, a “time-based relocation expected access time” algorithm is used, in which a nominal seek time is established, and profile table entries express a probability that an operation with a given latency above the nominal seek time will complete within the latency period. The expected access time is the latency plus the product of this probability and the time cost of a miss, i.e., the time of a single disk revolution.

Abstract: A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. The bus protocol is used to exchange snoop requests and addresses, data, coherency information and operational status between nodes in a manner that allows partial coherency results to be passed in parallel with a snoop request and address as an operation is forwarded along each ring. Each node combines it's own coherency results with the partial coherency results it received prior to forwarding the snoop request, address and updated partial coherency results to the next node on the ring. The protocol allows each node in the system to see the final coherency results without requiring the requesting node to broadcast these results to all the other nodes in the system.

Abstract: A prefetch mechanism includes a prefetch predictor table coupled to a prefetch control. The prefetch predictor table may include a plurality of locations configured to store a plurality of entries each indicative of a stride between a respective pair of memory requests. Each of the plurality of entries may be stored in a respective one of the plurality of locations dependent upon a value of an earlier stride. The prefetch control may be configured to prefetch an address based upon a given one of the plurality of entries in the prefetch predictor table.

Abstract: A storage device (1) communicating with a host computer and other storage devices through a network is characterized in that the storage device (1) secures memory buffers for temporarily storing data in a remote copy operation carried out between the storage devices. A network memory (100) in the storage device (1) includes an available buffer comprising a plurality of memory buffers and an in-use buffer also comprising a plurality of memory buffers. A buffer control unit (215) secures memory buffers of the available buffer as a reserved buffer having a reserved-buffer size specified in a buffer reservation request made by a storage management device (8) in response to the request. The buffer control unit (215) then allocates the memory buffers of the reserved buffer as the in-use buffer in response to a request received from the storage management device (8) to start a remote copy operation.

Abstract: A system and method to detect when a page access exception occurs on a subsequent part of a long operand processed out of order before the page is asynchronously marked valid by the operating system where the first request of the operand when later processed out of order after a subsequent buffer found no exception. In this case the instruction that encountered this situation is aborted and is re-executed with no page access exceptions. This prevents reporting improper delayed access exceptions on the operand data.

Abstract: In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data.

Abstract: A policy-based cache manager, including a memory storing a cache of digital content, a plurality of policies, and a policy index to the cache contents, the policy index indicating allowable cache content for each of a plurality of policies, a content scanner for scanning a digital content received, to derive a corresponding content profile, and a content evaluator for determining whether a given digital content is allowable relative to a given policy, based on the content profile. A method is also described and claimed.