Abstract: A process, apparatus, and system for evaluating a projected cache size implement and manage one or more projected cache lists that each contains directory entries corresponding to a projected cache size. The projected cache size may be either smaller or larger than the actual size of a cache installed in a computer system. Using the projected cache list entries, performance statistics such as cache hit ratio and average access time are tracked for each list. The process, apparatus, and system may calculate performance parameters that describe the performance specific to the actual cache list and each projected cache list. The resulting performance statistics may be used to formulate an optimization parameter to be communicated to a user or an administrator application.

Abstract: A method for managing host system power consumption is provided. The host system includes host memory and external memory. The method initiates with providing a processor in communication with a memory chip over a bus. The memory chip is external memory. Then, a usage measurement of the external memory is determined. If the usage measurement is below a threshold value, the method includes copying data from the memory chip to the host memory and terminating power to the memory chip. In one embodiment, the power is terminated to at least one bank of memory in the memory chip. In another embodiment, an amount of reduction of the external memory can be determined rather than a usage measurement. In yet another embodiment, an address map is reconfigured in order to maintain a contiguous configuration. A graphical user interface and a memory chip are provided also.

Abstract: A mechanism for caching Web services requests and responses, including testing an incoming request against the cached requests and associated responses is provided. The requests are selectively tested against the cached data in accordance with a set of policies. If a request selected hits in the cache, the response is served up from the cache. Otherwise, the request is passed to the corresponding Web-services server/application. Additionally, a set of predetermined cache specifications for generating request identifiers may be provided. The identifier specification may be autonomically adjusted by determining cache hit/cache miss ratios over the set of identifier specifications and over a set of sample requests. The set of specifications may then be sorted to reflect the performance of the respective cache specification algorithms for the current mix of requests.

Abstract: A memory system, memory module and memory device are described. The memory system includes a plurality of the memory modules connected in a series configuration on a first signal path. The first signal path and a second signal path carry memory control and data signals between the memory modules and a memory controller. The memory controller transmits and receives the control signals and data signals on the first and second signal paths. The first and second signal paths are connected together such that the memory modules are connected in a ring configuration. The control signals and data signals travel in opposite directions on the first and second signal paths. The first and second signal paths are shared by both the data signals and the control signals. The memory modules include multi-functional ports, each of which can receive both the control signals and the data signals and output the signals onto the connected signal paths.

Abstract: In a computer system with a non-segmented, region-based memory architecture, such as Intel IA-64 systems, two or more sub-systems share a resource, such as a virtual-to-physical address mapping and need to have overlapping regions of the virtual address space for accessing different physical addresses. Virtual addresses include a portion that is used to identify which region the issuing sub-system wants to access. For example, the region-identifying portion of virtual addresses may select a region register whose contents point to a virtual-to-physical address mapping for the corresponding region. To protect a second sub-system S2 from a first S1, whenever the S1 issues an address in a region occupied by S2, the region for the S2 is changed. This allows S1 to issue its addresses without change. In a preferred embodiment of the invention, S2 is a virtual machine monitor (VMM) and S1 is a virtual machine running on the VMM.

Abstract: A system and method for communicating a side effect of a data request, from a data server and through one or more caches, inline with a response to the request. Instead of sending a separate notification of the side effect (e.g., instructions to invalidate data cached in one or more caches), the notification is included in the response. As the response traverses caches on its way to the requestor, each cache applies the side effect with the proper timing. Thus, data invalidation may be performed prior to caching data included in the request and/or forwarding the response toward the requester. A final cache configured to serve the response to the requestor may remove the side effect notification before serving the response.

Abstract: A processor may include a stack file and an execution core. The stack file may include an entry configured to store an addressing pattern and a tag. The addressing pattern identifies a memory location within the stack area of memory. The stack file may be configured to link a data value identified by the tag stored in the entry to the speculative result of a memory operation if the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.

Abstract: A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves. The unit utilizes idle cycles occurring between consecutive requests to activate interleaves with pending requests.

Abstract: Provided are a method, system, and program for managing data. A scan request is received to remove data from cache included in a relationship after the relationship is established. Processing the scan request is delayed for a delay time in response to receiving the scan request. After the delay time, a determination is made as to whether a condition with respect to the scan request is satisfied. The scan request is processed to remove data from cache that is included in the relationship associated with the scan request if the condition is satisfied.

Abstract: CAM-based search engines and packet coprocessors include control logic that supports direct reads of information that summarizes the done status of multiple contexts being handled by the search engine device. This done status information may be maintained in dedicated registers that are configured to support high bandwidth utilization from a data port of the search engine device. The control logic may also be configured to generate interrupts or asynchronous signals that notify an issuing command source of context completion.

Abstract: A method and apparatus for operating a memory is presented. Information is stored in the memory based on a first time domain and information is read from the memory based on a second time domain. A cooperative relationship is maintained between a write pointer which points to memory locations, where data will be stored and a read pointer which points to memory locations, from which data will be read. A FIFO memory is presented which has memory locations and a register array is presented which stores a bit array that has bit locations. Each bit location in the bit array corresponds to a memory location in the memory. As the write pointer points to a memory location and data is stored in the memory location, a bit (e.g. flag) is set in the bit array. The Flag designates whether the data stored in the memory location is available for reading. Prior to reading information from the memory location, a test is made of the bit location that corresponds to the memory location.

Abstract: Tables (FIGS. 11 and 12) for stipulating information (WWN: WorldWide Name) for primarily identifying computers, information (GID: Group ID) for identifying a group of the computers and a logical unit number (LUN) permitting access from the host computer inside storage subsystem, in accordance with arbitrary operation method by a user, and for giving them to host computer. The invention uses management table inside the storage subsystem and gives logical unit inside storage subsystem to host computer group arbitrarily grouped by a user in accordance with the desired form of operation of the user, can decide access approval/rejection to the logical unit inside the storage subsystem in the group unit and at the same time, can provide the security function capable of setting interface of connection in the group unit under single port of storage subsystem without changing existing processing, limitation and other functions of computer.

Abstract: A method and apparatus for reducing instruction ITLB accesses. In one embodiment, the method may comprise generating a next virtual fetch address corresponding to an instruction fetch request and determining whether a current physical address translation is valid for the next virtual fetch address in response to its generation, wherein the determination may comprise detecting a change in the virtual page number of the next virtual fetch address relative to a virtual page number of a current virtual fetch address. The method may further comprise activating an ITLB circuit in response to determining that the current physical address translation is not valid for the next virtual fetch address, and performing the instruction fetch using the current physical address translation without activating the ITLB circuit in response to determining that the current physical address translation is valid for said next virtual fetch address.

Abstract: A method for storing data on a disk drive and checking the validity of data read from such disk drive. The method includes: transmitting the data from a source thereof for storage in the disk drive through a first transmission path and transmitting a CRC together with parity associated with such data for storage in a storage medium through a second path separate from the disk drive. The data stored on the disk drive is retrieved. A CRC associated with the retrieved data is determined. The determined CRC and the CRC stored in the storage medium are compared. With such method, if data and ins associated CRC are written into the incorrect location in the disk drive, during a read an error will be detected because the CRC of the read data will not match the CRC associated with the read data stored on the storage medium.

Abstract: A method for processing requests for information from a disc drive comprising: (a) receiving a plurality of requests, wherein each of the requests has application level information associated with it; (b) identifying a first group of the requests that fit within a time interval; (c) using a scheduling algorithm with disc information to schedule one of the requests in the first group; (d) adjusting the length of the time interval; (e) identifying another group of the requests that fit within the adjusted time interval; (f) using the scheduling algorithm to schedule one of the requests in the other group; and (g) repeating steps (d), (e) and (f). An apparatus that processes requests for information in accordance with the method is also provided.

Abstract: A method for optimizing a cache memory used for multitexturing in a graphics system is implemented. The graphics system comprises a texture memory, which stores texture data comprised in texture maps, coupled to a texture cache memory. Active texture maps for an individual primitive, for example a triangle, are identified, and the texture cache memory is divided into partitions. In one embodiment, the number of texture cache memory partitions equals the number of active texture maps. Each texture cache memory partition corresponds to a respective single active texture map, and is operated as a direct mapped cache for its corresponding respective single active texture map. In one embodiment, each texture cache memory partition is further operated as an associative cache for the texture data comprised in the partition's corresponding respective single active texture map. The cache memory is dynamically re-configured for each primitive.

Abstract: A subsystem logics partitioning and managing apparatus comprises a recognition unit for recognizing logical and physical resources that constitute a subsystem a partition definition table in which the logical and physical resources in the subsystem are assigned for each user at an interface level at which a storage configuration can be referenced by a storage management program an account table in which an account is set for each user-specific partition defined in the partition definition table a receiving unit for receiving a user account transmitted from an information processing unit and checking the received user account against the account table, to recognize a partition that corresponds to the user and a unit for outputting, at a GUI level, logical resources and physical resources that are contained in the recognized partition to an output interface as a resource configuration in the subsystem.

Abstract: A computer system in which a host computer is connected to a storage unit, the storage unit operating in a unit of a file. A file attribute control unit and the storage unit execute the processing being linked together so that, in response to a request from a client computer, the host computer executes a file attribute control program to add a particular attribute to the file, and that the storage unit operates in response to the attribute that is added.

Abstract: A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array stores an instruction sequence for execution by the memory device's controller circuit. The sequence can include instructions for testing of the memory device. The execution of the instruction sequence is initiated and the control circuit fetches each instruction from the scratch control array for execution. The results are then reported and/or stored in the scratch control array.

Abstract: The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories.