Abstract: In one aspect, the present disclosure describes a process for maintaining file allocation tables (FATs) for a volume of storage medium. The process includes triggering, by a write operation, modification of data in an existing sector of a data file by writing of data to a new sector of the storage medium. The process also includes writing revised used/unused sector information into one FAT and setting a variable indicative of a number of FATs (NOF) to a first value. The process additionally includes copying the one FAT to another FAT and re-setting the variable to a second value.

Abstract: A queuing architecture and method for scheduling disk drive access requests in a video server. The queuing architecture employs a controlled admission policy that determines how a new user is assigned to a specific disk drive in a disk drive array. The queuing architecture includes, for each disk drive, a first queue for requests from users currently receiving information from the server, and a second queue for all other disk access requests, as well as a queue selector selecting a particular first queue or second queue for enqueuing a request based on the controlled admission policy. The controlled admission policy defines a critical time period such that if a new user request can be fulfilled without causing a steady-state access request for a particular disk drive to miss a time deadline, the new user request is enqueued in the second queue of the particular disk drive; otherwise, the controlled admission policy enqueues the new user request in a second queue of another disk drive.

Abstract: This invention is a system and method for assisting the performance of incremental copying of data in a data storage environment and includes a tracking mechanism. In one embodiment, the tracking mechanism is implemented in such a way that it is able to track changes while allowing access to production data by carrying out unique methodology. In other embodiments, implementations include a system, a computer program product, or an apparatus, wherein each embodiment is configured for carrying out the steps involved in the methodology.

Abstract: A computer system embedding buffers therein for performing a digital signal processing (DSP) data access operation includes a DSP core,a data cache, first and second buffer modules, an external memory and a central processing unit (CPU) core. The CPU core executes instructions and the DSP core processes data in accordance with the instructions. The data cache stores temporary data associated with the DSP core. The first buffer module stores input data received by the DSP core while the second buffer module stores output data provided from the DSP core. The external memory stores the temporary data, the input data, and the output data, wherein the input and output data are received by and provided from the DSP core in series through the first and second buffer modules without going through the data cache.

Abstract: A vector information processing apparatus has a CPU comprising a plurality of asynchronously operating units, a main memory for storing data, and a main memory controller for controlling the writing of data in the main memory. The main memory controller has a VSC address buffer for holding a storage address in the main memory for each element designated by a vector scatter instruction. The main memory controller is arranged to inhibit the outputting of a writing permission signal for the main memory which is generated according to a writing request for writing an element having a smaller element number, which has the same storage address as the storage address and which has not been processed in a sequence of element numbers, of writing requests for writing elements in the main memory which are issued respectively from the asynchronously operating units according to a vector scatter instruction.

Abstract: Circuits are described that can detect the presence or absence of an input number in a pre-defined list of numbers, and provide an index into the list for a matching number. The elements of the list of numbers may be individual numbers, or sets of numbers within a range of numbers.

Abstract: A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient time available to perform the requested operation. If there is sufficient time available and the device manager is in an exclusive mode, the state of the memory device is checked to determine if it is currently executing an operation. If so, this operation is suspended and the requested operation is issued to the memory device. The device manager polls the memory device to determine when the requested operation has been completed. Upon completion, the interrupts are re-enabled and control of the memory device is returned to the system.

Abstract: A system and method for communicating a side effect of one data request, or other event, as part of a response to another data request or event. The side effect may include notification of the invalidation of cached data, from an upstream cache to a downstream cache. The upstream cache may store invalidation notifications as they are generated or received, and as responses to data requests are sent downstream, piggyback or merge one or more notifications with a response. This scheme avoids the need to open separate communication connections using specified invalidation accounts and passwords.

Abstract: A microcomputer includes (a) a central processing unit, (b) a bus controller electrically connected to the central processing unit through a first bus, (c) a command cache electrically connected to the central processing unit through a second bus, and to the bus controller through a third bus, and (d) a command memory electrically connected to the second bus through a fourth bus, and storing interruption handling routine therein.

Abstract: A cache memory system including a cache memory employing a tag including associated touch bits. The system includes a first cache memory subsystem having a first cache storage and a second cache memory subsystem including a second cache storage. The first cache storage may store a first plurality of cache lines of data. The second cache storage may store a second plurality of cache lines of data. Further the second cache memory subsystem includes a tag storage which may store a plurality of tags each corresponding to a respective cache line of the second plurality of cache lines. In addition, each of said plurality of tags includes an associated bit indicative of whether a copy of the corresponding respective cache line is stored within the first cache memory subsystem.

Abstract: A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.

Abstract: Controlling access to a control register of a microprocessor. A method of controlling access to a control register such as CR3, for example, of a processor having a normal execution mode and a secure execution mode may include storing address translation table information in the control register, allowing a software invoked write access to modify the address translation table information during the normal execution mode and selectively inhibiting the software invoked write during the secure execution mode.

Abstract: A memory module device for use in a high frequency operation provides for ease in synchronization. In one example, the memory module includes integrated buffers, each having first and second data ports connected to respective data buses in a point-to-point configuration, such that data input through either data port of the first and second data ports is transferred to the memory device and is simultaneously output through the other data port of the first and second data ports. The integrated buffers each further include first and second command address ports connected to respective command address buses in a point-to-point configuration, such that a command address signal input through either port of the first and second command address ports is transferred to the memory device and simultaneously output through the other command address port of the first and second command address ports.

Abstract: Improved file tracking methods and file re-positioning or file defragmenting mechanisms are disclosed for use with a differential rate memory device which has allocatable storage units disposed in regions of comparatively faster data access and of comparatively slower data access for storing retrievable data file contents in such regions.

Abstract: The present invention provides a system for managing cache replacement eligibility. A first address register is configured to request an address from an L1 cache. An L1 cache is configured to determine whether a requested address is in the L1 cache and, in response to a determination that a requested address is not in the L1 cache, is further configured to transmit the requested address to a range register coupled to the L1 cache. The range register is configured to generate a class identifier in response to a received requested address and to transmit the requested address and class identifier to a replacement management table coupled to the range register. The replacement management table is configured to generate L2 tag replacement control indicia in response to a received requested address and class identifier. An L2 address register is coupled to the first address register and configured to request an address from an L2 cache.

Abstract: A storage system and method for prestaging data in a cache based on relative changes in the frequency of data access and relative changes in the effectiveness of previous prestage operations. The relative changes in the frequency of data access are determined by storing statistics of data access to all regions in the system and comparing recent access statistics to the stored data. Access statistics include data location, I/O size and access frequency. The relative changes in the effectiveness of previous prestage operations are detected by recording the number of previous prestaging operations for a region, recording the number of I/O requests for data that has been prestaged, and dividing the number of I/O requests for previously prestaged data in a region during a time period by the number of previous prestage operations for the region during the same time.

Abstract: In one embodiment of the present invention, a method includes setting an update to data of a memory to a valid status, and changing an original version of the data to a backup status.

Abstract: The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

Abstract: The present invention provides a storage system and a method of controlling the storage system, in which a second site rapidly resumes system process when a first site is damaged. The storage system comprises a first site including a first storage device, a second site including a second storage device, and a third site including a third storage device, and the method of controlling the storage system comprises a step of making a logical volume of the second storage device consistent with a logical volume of the first storage device by remotely copying only the differential data between the logical volume of the first storage device and the logical volume of the second storage device from a logical volume of the third storage device to the logical volume of the second storage device when the first site is damaged.

Abstract: A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.