Abstract: While a large amount of files can be intensively managed, the capacity scalability is limited by the number of magnetic disk drives and the number of magnetic tape drives which can be connected to a system, thereby failing to provide satisfactory long-term management for a large amount of information which increases more and more over time. A storage system of the present invention is designed for connection with a heterogeneous storage which can be controlled by the storage system, and creates file systems in a storage area reserved within the storage system and in a storage area provided by the heterogeneous storage.

Abstract: A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher includes a prediction generator configured to generate a prediction that is unpatternable to an address. Also, the prefetcher also can include a target cache coupled to the prediction generator to maintain the prediction in a manner that determines a priority for the prediction. In another embodiment, the prefetcher can also include a priority adjuster. The priority adjuster sets a priority for a prediction relative to other predictions. In some cases, the placement of the prediction is indicative of the priority relative to priorities for the other predictions. In yet another embodiment, the prediction generator uses the priority to determine that the prediction is to be generated before other predictions.

Abstract: An apparatus for data storage includes a cluster of NFS servers. Each server has network ports for incoming file system requests and cluster traffic between servers. The apparatus includes a plurality of storage arrays in communication with the servers. The servers utilize a striped file system for storing data. A method for data storage. A method for establishing storage for a file. A method for removing a file from storage. A method for reading data in a file. A method for writing data in a file.

Abstract: A storage device (1) communicating with a host computer and other storage devices through a network is characterized in that the storage device (1) secures memory buffers for temporarily storing data in a remote copy operation carried out between the storage devices. A network memory (100) in the storage device (1) includes an available buffer comprising a plurality of memory buffers and an in-use buffer also comprising a plurality of memory buffers. A buffer control unit (215) secures memory buffers of the available buffer as a reserved buffer having a reserved-buffer size specified in a buffer reservation request made by a storage management device (8) in response to the request. The buffer control unit (215) then allocates the memory buffers of the reserved buffer as the in-use buffer in response to a request received from the storage management device (8) to start a remote copy operation.

Abstract: A data caching method and a computer-readable medium storing a program executing the method used in a cache system where a data replacing parameter is used for a data replacement rule, are provided to assist determining whether a user data has to be replaced or not. The data caching method and the program rely on the cache system to determine whether to replace the user data when the resource consumed in fetching the user data is lower than a predetermined level. However, when the resource consumed in fetching the user data is higher or equal to the predetermined level, the value of the data replacing parameter mentioned above is replaced within a predetermined period, such that the user data could be maintained in the cache system.

Abstract: A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset of the predictions is either issued to access a memory or filtered out as redundant. In another embodiment, an exemplary prefetcher predicts accesses to a memory. The prefetcher comprises a speculator for generating a number of predictions and a prediction inventory, which includes queues each configured to maintain a group of items. The group of items typically includes a triggering address that corresponds to the group. Each item of the group is of one type of prediction. Also, the prefetcher includes an inventory filter configured to compare the number of predictions against one of the queues having the either the same or different prediction type as the number of predictions.

Abstract: An apparatus having one or more cache agents and a protocol agent is disclosed. The protocol agent is coupled to the one or more cache agents to receive events corresponding to cache operations from the one or more cache agents to maintain ordering with respect to the cache operation events. The protocol agent includes a structure to handle conflict resolution.

Abstract: There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system, by providing functions by program products in each division unit of a storage subsystem. The storage management system has a program-product management table stored in a shared memory in the storage subsystem and showing presence or absence of the program products, which provide management functions of respective resources to respective SLPRs. At the time of executing the management functions by the program products in the SLPRs of users in accordance with instructions from the users, the storage management system is referred to and execution of the management function having no program product is restricted.

Abstract: A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory receives memory request identifiers and stores the memory request identifiers. A packet tracker receives remote memory responses and associates each remote memory response with a memory request identifier and removes the memory request identifier from the packet memory. A multiplexor receives remote memory responses and local memory responses. The multiplexor selects an output responsive to a control signal. Arbitration control logic is coupled to the multiplexor and the packet memory and develops the control signal to select a memory response for output.

Abstract: A system and method efficiently guarantees data consistency to clients for one or more data containers stored on a plurality of volumes configured as a striped volume set (SVS) and served by a plurality of nodes connected as a cluster. Data consistency guarantees of data containers stored on the SVS is generally provided by delegating to data volumes (DVs) sufficient authority to autonomously service input/output (I/O) requests directed to the containers using attributes, such as timestamps, of the containers. Specifically, a DV is only allowed to service I/O requests, e.g., read and write operations, to a data container, such as a file, if it has a valid ticket book for the file. A DV requests and is granted the ticket book from a container attribute volume (CAV) on a per-file basis.

Abstract: A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient time available to perform the requested operation. If there is sufficient time available and the device manager is in an exclusive mode, the state of the memory device is checked to determine if it is currently executing an operation. If so, this operation is suspended and the requested operation is issued to the memory device. The device manager polls the memory device to determine when the requested operation has been completed. Upon completion, the interrupts are re-enabled and control of the memory device is returned to the system.

Abstract: A transactional memory implementation has been developed that is capable of coordinating concurrent hardware transactional memory (HTM) and software transactional memory (STM) transactions over a unified transactional memory space. Some implementations employ hardware transactional memory, if available or suitable, to improve performance. Some exploitations include a hardware transactional memory in which, or for which, hardware-mediated transactions are augmented to include within their transactional scope (or mechanism) one or more additional transactional locations that facilitate coordination with concurrently executing software-mediated transactions (if any).

Abstract: A method of controlling a content addressable memory (CAM) device. A data structure is generated that specifies (i) a prioritized set of rules and (ii) storage locations within the CAM device for one or more match clauses of each of the rules. A new rule having a specified priority is recorded in the data structure. Candidate storage locations within the CAM device are identified within the CAM device for the match clauses of each of the rules having a lower priority than the new rule. The candidate storage locations are compared with the storage locations specified by the data structure. Each match clause for which the candidate storage location does not match the specified storage location is stored in the CAM device.

Abstract: A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

Abstract: One embodiment of the present invention is directed to providing a software layer that provides a Content Addressable Storage (CAS) capability in a computer system in which the content units are ultimately stored on a block I/O storage system. An application program may issue access requests to content units referring to them via a content address, and the software layer can convert such access requests to block I/O commands to be processed by the block I/O storage system. Thus, a CAS capability can be provided despite the absence of a storage system that provides such a capability natively.

Abstract: A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. Each active device in one of the plurality of nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address and associated information that identifies a translation function. The memory subsystem in the one of the plurality of nodes is configured to apply the translation function identified in the information to the global address to generate a local physical address.

Abstract: A method, system and computer-readable medium are provided for updating memory devices in a multi-processor computer system. A computer program is launched on a first processor in the multi-processor computer system. The program contains update code for updating memory devices in the computer system. Each processor in the computer system is associated with a memory device. Processors only have access to the memory devices with which they are associated. The program launched on the first processor determines the identity of additional processors associated with memory devices inaccessible by the first processor. The first processor then sends the code contained in the program to the identified additional processors. Finally, the update code is executed on the first processor and the identified additional processors to update the memory devices associated with each processor in the multi-processor computer system.

Abstract: A subsystem logics partitioning and managing apparatus comprises a recognition unit for recognizing logical and physical resources that constitute a subsystem a partition definition table in which the logical and physical resources in the subsystem are assigned for each user at an interface level at which a storage configuration can be referenced by a storage management program an account table in which an account is set for each user-specific partition defined in the partition definition table a receiving unit for receiving a user account transmitted from an information processing unit and checking the received user account against the account table, to recognize a partition that corresponds to the user and a unit for outputting, at a GUI level, logical resources and physical resources that are contained in the recognized partition to an output interface as a resource configuration in the subsystem.

Abstract: A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. An active device included in one of the nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address identifying a coherency unit. A portion of the global address identifies a translation function. A memory subsystem included in the node is configured to perform the translation function identified by the portion of the global address on an additional portion of the global address in order to obtain a local physical address of the coherency unit. Each active device included in the node is configured to use the portion of the global address identifying the translation function when determining whether a local copy of the coherency unit is currently stored in a cache associated with that active device.

Abstract: A data memory circuit is provided. In one embodiment, the data memory circuit comprises a plurality of addressable memory cells, a command decoding device for decoding external commands and a control device for controlling or initiating operations for the operation of the data memory circuit in each case in a manner dependent on the decoded commands. The memory circuit has critical operating states in which the execution of specific commands is impermissible resulting in the course of specific operations in the data memory circuit, wherein a command buffer device buffer-stores commands received during the duration of their impermissibility and releases them for execution after the end of their impermissibility.