Patents Examined by Duy Deo
  • Patent number: 10079382
    Abstract: A method of forming an electrode in an electrochemical battery comprises: coating a reticulated substrate with a conductive material; curing the reticulated substrate coated with the conductive material; and electroplating the reticulated substrate coated with the conductive material with a desired metal material.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 18, 2018
    Inventors: Alvin Snaper, Jonathan Jan
  • Patent number: 10049876
    Abstract: A method for semiconductor processing includes forming a trilayer resist structure having a middle layer disposed between a top layer and a bottom layer. The top layer is removed from a first region to expose the middle layer in the first region, and the middle layer and the bottom layer are removed in the first region to expose a structure to be processed. The top layer in a second region is also removed with the bottom layer in the first region. The first region is filled to protect the structure in the first region. The middle layer is removed in the second region while the first region remains protected. The structures in the first region and structures in the second region are exposed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Muthumanickam Sankarapandian, Soon-Cheon Seo, Indira P. Seshadri, John R. Sporre
  • Patent number: 10032605
    Abstract: Methods and apparatus for processing a substrate in a multi-frequency plasma processing chamber are disclosed. The base RF signal pulses between a high power level and a low power level. Each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined power level and a second predefined power level as the base RF signal pulses. Alternatively or additionally, each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined RF frequency and a second predefined RF frequency as the base RF signal pulses. Techniques are disclosed for ascertaining in advance of production time the first and second predefined power levels and/or the first and second predefined RF frequencies for the non-base RF signals.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: July 24, 2018
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Bradford J. Lyndaker
  • Patent number: 10008384
    Abstract: A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 26, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, John Hautala, Adam Brand, Huixiong Dai
  • Patent number: 10002754
    Abstract: Electric charging of a substrate caused by a friction between a fluid and a surface of the substrate being rotated can be suppressed. At least a part of a surface insulating layer (thermal oxide film) on a peripheral portion of a substrate W is removed, and an underlayer (silicon wafer) having higher conductivity than a material of the surface insulating layer is exposed. Then, a process is performed on the substrate while holding and rotating the substrate by a substrate holding device. Here, at least a portion of the substrate holding device which comes into contact with the underlayer is made of a conductive material. In performing the process on the substrate, an electric charge generated in the surface insulating layer of the substrate is removed via the underlayer and the substrate holding device.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 19, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Keiichi Tanaka
  • Patent number: 9994737
    Abstract: Provided are slurry compounds for polishing an SOH organic layer and methods of fabricating a semiconductor device using the same. The slurry compound may include a polishing particle, an oxidizing agent including at least one selected from the group consisting of a nitrate, a sulfate, a chlorate, a perchlorate, a chlorine, and a peroxide, and a polishing accelerator.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkyun Kim, Yun-Jeong Kim, SeungHo Park
  • Patent number: 9966273
    Abstract: There is provided a plasma etching method. The plasma etching method includes generating plasma, by using a first high frequency power output from a first high frequency power supply, from a first processing gas that contains fluorine-containing gas, thereby etching a laminated film of a silicon oxide film and a silicon nitride film through the generated plasma, and generating plasma, by using the first high frequency power, from a second processing gas that contains bromine-containing gas, thereby etching the laminated film through the generated plasma.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 8, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Wataru Takayama, Sho Tominaga, Yoshiki Igarashi
  • Patent number: 9959890
    Abstract: A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL. The second etching process can also etch a portion of the magnetoresistive stack. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Raberg, Andreas Strasser, Hermann Wendt, Klemens Pruegl
  • Patent number: 9938635
    Abstract: A method for producing a component includes joining individual wall parts, especially for producing a melting crucible for use at a high operating temperature in a crucible-pulling method for quartz glass, wherein at least two wall parts of a refractory metal or of a base alloy of a refractory metal are provided, butt-joined to form a joint and joined together by sintering at a temperature above 1500° C. to form the component. A sealant is inserted into the joint to provide a component of improved tightness and to ensure improved sintering of the individual parts of the component. A component produced according to the method, particularly a melting crucible, particularly in a crucible pulling method for quartz glass, has the joint between the butt-joined walls closed in a gas-tight manner by a sealant.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 10, 2018
    Assignee: Heraeus Quarzglas GmbH & Co. KG
    Inventors: Boris Gromann, Nigel Whippey, Christian Schenk
  • Patent number: 9941111
    Abstract: According to various embodiments, a method for processing a semiconductor layer may include: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; introducing the etch plasma into the processing chamber to remove a native oxide layer from a surface of the semiconductor layer and at most a negligible amount of semiconductor material of the semiconductor layer; and, subsequently, depositing a dielectric layer directly on the surface of the semiconductor layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 10, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gerhard Schmidt, Markus Kahn, Christian Maier, Philipp Koch, Juergen Steinbrenner
  • Patent number: 9932690
    Abstract: A device for producing a single crystal by crystallizing the single crystal in a melt zone, comprising a housing, an inductor for generating heat in the melt zone, a reheater which surrounds and applies thermal radiation to the crystallizing single crystal, and a separating bottom which delimits downward an intermediate space between the reheater and a wall of the housing at a lower end of the reheater.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: April 3, 2018
    Assignee: SILTRONIC AG
    Inventors: Georg Raming, Ludwig Altmannshofer
  • Patent number: 9911448
    Abstract: A perpendicular magnetic recording medium according to an embodiment includes a substrate and perpendicular magnetic recording layer. The perpendicular magnetic recording layer includes a recording portion and non-recording portion. The recording portion has patterns regularly arranged in the longitudinal direction, and includes magnetic layers containing Fe or Co and Pt as main components, and at least one additive component selected from Ti, Si, Al, and W. The non-recording portion includes oxide layers formed by oxidizing the side surfaces of the magnetic layers, and nonmagnetic layers formed between the oxide layers.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: March 6, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Iwasaki, Kazutaka Takizawa, Akira Watanabe, Kaori Kimura, Akihiko Takeo
  • Patent number: 9911620
    Abstract: Methods of selectively etching silicon nitride on a semiconductor substrate by providing silicon to the plasma to achieve high etch selectivity of silicon nitride to silicon-containing materials are provided. Methods involve providing silicon from a solid or fluidic silicon source or both. A solid silicon source may be upstream of a substrate, such as at or near a showerhead of a process chamber, or in a remote plasma generator. A silicon gas source may be flowed to the plasma during etch.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: March 6, 2018
    Assignee: Lam Research Corporation
    Inventors: Helen H. Zhu, Linda Marquez, Faisal Yaqoob, Pilyeon Park, Ivan L. Berry, III, Ivelin A. Angelov, Joon Hong Park
  • Patent number: 9911582
    Abstract: The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Banqiu Wu, Ajay Kumar, Kartik Ramaswamy, Omkaram Nalamasu
  • Patent number: 9896778
    Abstract: An apparatus for producing SiC single crystals where the quality of the SiC single crystals is improved, and a production method using such an apparatus are provided. The apparatus for producing SiC single crystals according to an embodiment of the present invention is employed to produce an SiC single crystal by the solution growth method. The production apparatus includes a crucible and a support shaft. The crucible accommodates an Si—C solution. The support shaft supports the crucible. The support shaft includes a heat removing portion for removing heat from a bottom portion of the crucible. The heat removing portion includes one of (a) a contact portion having a thermal conductivity not less than that of the bottom portion and contacting at least a portion of the bottom portion and (b) a space adjacent to at least a portion of the contact portion or the bottom portion.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 20, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kazuhito Kamei, Kazuhiko Kusunoki, Motohisa Kado, Hironori Daikoku, Hidemitsu Sakamoto
  • Patent number: 9896762
    Abstract: A method of forming layers of film on a patterned surface, including depositing a film on the patterned surface during a PEALD/PPECVD process in a processing apparatus and etching the film during the etching process in the processing apparatus.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 20, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventor: Toshihisa Nozawa
  • Patent number: 9887097
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques. In certain implementations the protective coating is fluorinated.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 6, 2018
    Assignee: Lam Research Corporation
    Inventor: Eric A. Hudson
  • Patent number: 9868902
    Abstract: The disclosure is related to a composition for etching, a method for manufacturing the composition, and a method for fabricating a semiconductor using the same. The composition may include a first inorganic acid, at least one of silane inorganic acid salts produced by reaction between a second inorganic acid and a silane compound, and a solvent. The second inorganic acid may be at least one selected from the group consisting of a sulfuric acid, a fuming sulfuric acid, a nitric acid, a phosphoric acid, and a combination thereof.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: January 16, 2018
    Assignee: SOULBRAIN CO., LTD.
    Inventors: Jin Uk Lee, Jae Wan Park, Jung Hun Lim
  • Patent number: 9870932
    Abstract: A method for etching a substrate and removing byproducts includes a) setting process parameters of a processing chamber for a selective dry etch process; b) setting process pressure of the processing chamber to a first predetermined pressure in a range from 1 Torr to 10 Torr for the selective dry etch process; c) selectively etching a first film material of a substrate relative to a second film material of the substrate in the processing chamber during a first period; d) lowering pressure in the processing chamber to a second predetermined pressure that is less than the first predetermined pressure by a factor greater than or equal to 4; and e) purging the processing chamber at the second predetermined pressure for a second period.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 16, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Pilyeon Park, Joydeep Guha
  • Patent number: 9863060
    Abstract: Method for manufacturing a single crystal according to a CZ method, including: pre-examining a correlation between an Al/Li ratio in a quartz raw material powder used for producing the quartz crucible, a use time of the crucible, a devitrification ratio at the use time, and occurrence or nonoccurrence of melt leakage attributable to the devitrification part; setting a range of the devitrification ratio of the quartz crucible in order not to generate the melt leakage, and determining a maximum use time of the quartz crucible according to the Al/Li ratio so as to fall within the set range of the ratio, on the basis of the correlation; and growing the single crystal by using the quartz crucible in the range of the maximum use time. This provides a manufacturing method which can efficiently use a quartz crucible to grow a single crystal while preventing occurrence of melt leakage.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: January 9, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yuuichi Miyahara, Shou Takashima, Yasuhiko Sawazaki, Atsushi Iwasaki