Patents Examined by Duy Deo
  • Patent number: 9797062
    Abstract: The present invention aims at providing a zone melting furnace thermal field with a dual power heating function and a heat preservation method. The zone melting furnace thermal field comprises a primary heating coil and an auxiliary heater, wherein the auxiliary heater has a wavy appearance bent repeatedly up and down and forms a circular loop by surrounding in the horizontal direction, wherein both end parts of the auxiliary heater are provided with ports and are connected with an auxiliary heating power supply through cables; and the auxiliary heating power supply is also sequentially connected with a data analysis module and an infrared temperature measuring instrument through single lines. The present invention can solve the problem of single crystal rod cracking caused by unreasonable distribution of the thermal field and overlarge thermal stress in the growth process of zone-melted silicon single crystals over 6.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: October 24, 2017
    Assignee: ZHEJIANG JINGSHENG M & E CO., LTD
    Inventors: Jianwei Cao, Penggen Ouyang, Dantao Wang, Linjian Fu, Mingjie Chen, Gang Shi, Minxiu Qiu
  • Patent number: 9797068
    Abstract: Relates to a method of producing a semiconductor crystal having generation of a defect suppressed in the semiconductor single crystal. The production method includes the steps of: forming a boron oxide film on the inner wall of a growth container having a bottom section and a body section continuous to the bottom section; bringing the boron oxide film into contact with boron oxide melt containing silicon oxide to form a boron oxide film containing silicon oxide on the inner wall of the growth container; forming raw material melt above seed crystal placed in and on the bottom section of the growth container; and solidifying the raw material melt from the seed crystal side to grow a semiconductor single crystal.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: October 24, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Sakurada, Tomohiro Kawase, Yoshiaki Hagi
  • Patent number: 9790618
    Abstract: The present invention relates to a method and apparatus for growing sapphire single crystals, and more particularly to a method and apparatus for growing sapphire single crystals in which a high quality, long single crystal can be obtained within a short period of time upon the use of a long rectangular crucible and a long seed crystal extending in a c-axial direction. Use of the method and apparatus for growing sapphire single crystals according to the present invention can uniformly maintain the horizontal temperature at the inside of the crucible despite the use of a rectangular crucible, thereby obtaining a high-quality single crystal as well decreasing the possibility of a failure in the growth of the single crystal.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: October 17, 2017
    Assignee: CRISTECH CO., LTD.
    Inventor: Jun Tae Ahn
  • Patent number: 9790401
    Abstract: The present disclosure relates to abrasive particles, a polishing slurry and a fabricating method of the abrasive particles. The fabricating method of abrasive particles in accordance with an exemplary embodiment of the present disclosure includes preparing a precursor solution in which a first precursor is mixed with a second precursor that is different from the first precursor, preparing a basic solution, mixing the basic solution with the precursor solution and forming a precipitate, and washing abrasive particles synthesized by precipitation.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: October 17, 2017
    Assignee: UBMATERIALS INC.
    Inventor: Jin Hyung Park
  • Patent number: 9786504
    Abstract: A method for forming a patterned layer is provided. The method comprises forming a first material layer over a first substrate, forming a photoresist layer on the first material layer, wherein the photoresist layer includes at least one island portion and a spacing surrounding a lateral portion of the island portion, trimming the island portion to enlarge the spacing, forming a second material layer filled in the enlarged spacing and surrounding the trimmed island portion, removing the trimmed island portion to form a first opening passing through the second material layer and exposing a portion of the first material layer, and removing the exposed portion of the first material layer through the first opening to form a second opening in the first material layer.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: October 10, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Kuo-Yao Chou
  • Patent number: 9777398
    Abstract: Systems and method for creating crystalline parts having a desired primary and secondary crystallographic orientations are provided. One embodiment may take the form of a method of manufacturing a part having a crystalline structure. The method includes melting aluminum oxide and drawing the melted aluminum oxide up a slit. Additionally, the method includes orienting the seed crystal relative to a growth apparatus such that a crystalline structure grows having a desired primary plane and a desired secondary plane orientation. Moreover, the method includes pulling the crystal as it forms to create a ribbon shaped crystalline structure and cutting a part from the crystalline structure.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: October 3, 2017
    Assignee: APPLE INC.
    Inventors: Benjamin J. Pope, Christopher D. Prest, Dale N. Memering, Scott A. Meyers
  • Patent number: 9777395
    Abstract: An apparatus for growing a silicon single crystal according to embodiments includes a chamber including a crucible accommodating silicon melt; a support shaft rotating and lifting the crucible while supporting the crucible; a main heater part for applying heat to the crucible side, the heater disposed beside the crucible; an upper heat insulation member located over the crucible; and upper heater parts located at a lower end portion of the upper heat insulation member, wherein the upper heater parts have diameters different from each other with respect to a center of the crucible, and include a plurality of ring-shaped heaters which are spaced apart from each other. Due to the individually controllable upper heater parts, a uniform thermal environment can be provided for silicon melt accommodated in a crucible, and localized solidification of the silicon melt can be prevented so that the quality of a silicon single crystal and the ingot pulling speed can be readily controlled.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 3, 2017
    Assignee: LG Siltron, Inc.
    Inventor: Su-In Jeon
  • Patent number: 9777400
    Abstract: A method for producing a single crystal includes a step of placing a source material powder and a seed crystal within a crucible, and a step of growing a single crystal on the seed crystal. The crucible includes a peripheral wall part and a bottom part and a lid part that are connected to the peripheral wall part to close the openings of the peripheral wall part, the lid part having a holder that holds the seed crystal. The bottom part has a connection region connected to the peripheral wall part and a thick region that is thicker than the connection region and that surrounds a central axis passing through a center of gravity of orthogonal projection of the bottom part, the orthogonal projection being formed on a plane perpendicular to a growth direction of the single crystal, the central axis extending in the growth direction of the single crystal.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: October 3, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shunsaku Ueta, Tsutomu Hori, Akira Matsushima
  • Patent number: 9779941
    Abstract: In a method of forming patterns of a semiconductor device, an object layer is formed on a substrate. A plurality of guiding pillars and at least one guiding dam are formed on the object layer. A self-aligned layer including a block copolymer is formed in a space between the guiding pillars and the guiding dam, such that first blocks aligned around the guiding pillars and second blocks aligned around the guiding dam are formed. A trim pattern at least partially covering the guiding dam is formed. The first blocks are transferred in the object layer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Han Park
  • Patent number: 9777393
    Abstract: Process for fabricating a thin single-crystalline layer n, including steps of: a) providing a support substrate n, b) placing a seed sample n, c) depositing a thin layer n so as to form an initial interface region n including a proportion of seed sample n and a proportion of thin layer n, the proportion of seed sample n decreasing from the first peripheral part n towards the second peripheral part n, e) providing an energy input to the initial interface region n contiguous to the first peripheral part n so as to liquefy a portion n of the thin layer and form a solid/liquid interface region n, and f) gradually moving the energy input away from the seed sample n so as to solidify the portion n so as to gradually move the solid/liquid interface region n.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Lamine Benaissa
  • Patent number: 9777397
    Abstract: Systems and methods for continuous sapphire growth are disclosed. One embodiment may take the form of a method including feeding a base material into a crucible located within a growth chamber, heating the crucible to melt the base material and initiating crystalline growth in the melted base material to create a crystal structure. Additionally, the method includes pulling the crystal structure away from crucible and feeding the crystal structure out of the growth chamber.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 3, 2017
    Assignee: APPLE INC.
    Inventors: Dale N. Memering, Scott A. Myers
  • Patent number: 9777399
    Abstract: A method for producing a SiC single crystal, comprising using a Si—C solution having a temperature gradient in which the temperature decreases from the interior toward the surface to grow a SiC single crystal from a seed crystal substrate, wherein the Si—C solution includes Si and Cr, the boron density difference Bs?Bg between the boron density Bs in the seed crystal substrate and the boron density Bg in the growing single crystal is 1×1017/cm3 or greater, the chromium density difference Crg?Crs between the chromium density Crs in the seed crystal substrate and the chromium density Crg in the growing single crystal is 1×1016/cm3 or greater, and the nitrogen density difference Ng?Ns between the nitrogen density Ns in the seed crystal substrate and the nitrogen density Ng in the growing single crystal is 3.5×1018/cm3 to 5.8×1018/cm3.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: October 3, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Katsunori Danno
  • Patent number: 9778620
    Abstract: Method for creating a flexible, multistable element (5): a silicon component (S) is etched with a beam (P) connecting two ends (E1, E2) of a rigid mass (MU) having a cross-section more than ten times that of said beam (P), SiO2 is grown at 1100° C. for a duration adjusted to obtain, on said beam (P), a first ratio (RA) of more than 1 between the section of a first peripheral layer (CP1) of SiO2, and that of a first silicon core (A1), and, on said mass (MU), a second ratio (RB) between the section of a second peripheral layer (CP2) of SiO2 and that of a second silicon core (A2), which is less than a hundredth of said first ratio (RA); cooling to ambient temperature is performed, to deform said beam (P) by buckling when said mass (MU) cools and contracts more than said beam (P).
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 3, 2017
    Assignee: NIVAROX-FAR S.A.
    Inventors: Marc Stranczl, Thierry Hessler
  • Patent number: 9777401
    Abstract: A method for producing a single crystal includes a step of placing a source material powder and a seed crystal within a crucible; and a step of growing a single crystal on the seed crystal. The crucible includes a peripheral wall part and a bottom part and a lid part that are connected to the peripheral wall part to close the openings of the peripheral wall part. In the step of growing the single crystal on the seed crystal, the crucible is disposed on a spacer so as to form a space starting directly below an outer surface of the bottom part, and the peripheral wall part and an auxiliary heating member that is placed so as to face the outer surface of the bottom part with the space therebetween are heated by induction heating to sublime the source material powder to cause recrystallization on the seed crystal.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: October 3, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shunsaku Ueta, Tsutomu Hori, Akira Matsushima
  • Patent number: 9776875
    Abstract: The present invention relates to a method for producing graphene on a face-centered cubic metal catalyst having a plane oriented in one direction, and more particularly to a method of producing graphene on a metal catalyst having the (100) or (111) crystal structure and a method of producing graphene using a catalyst metal foil having a single orientation, obtained by electroplating a metal catalyst by a pulse wave current and annealing the metal catalyst. The invention also relates to a method of producing graphene using a metal catalyst, and more particularly to a method of producing graphene, comprising the steps of: alloying a metal catalyst with an alloying element; forming step structures on the metal catalyst substrate in an atmosphere of a gas having a molecular weight of carbon; and supplying hydrocarbon and hydrogen gases to the substrate. On unidirectionally oriented metal catalyst prepared according to the present invention, graphene can be grown uniformly and epitaxially.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: October 3, 2017
    Assignee: SRC Corporation
    Inventors: Kang Hyung Kim, Kwan Sub Maeng, Chol Woo Park, Se Won Cha, Se Youn Hong, Byung He Hong, Myung Hee Jung, Kyung Eun Kim, Su Beom Park
  • Patent number: 9777396
    Abstract: A method for producing a crystal, according to the present invention, where the lower surface of a seed crystal which is rotatably arranged and made of silicon carbide is brought into contact with a solution of silicon solvent containing carbon in a crucible which is rotatably arranged and the seed crystal is pulled up and a crystal of silicon carbide is grown from the solution on the lower surface of the seed crystal, comprising the steps of bringing the lower surface of the seed crystal into contact with the solution in a contact step, rotating the seed crystal in a seed crystal rotation step, rotating the crucible in a crucible rotation step, and stopping rotation of the crucible, while the seed crystal is rotated in the state in which the lower surface of the seed crystal is in contact with the solution, in a deceleration step.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 3, 2017
    Assignee: KYOCERA CORPORATION
    Inventors: Chiaki Domoto, Katsuaki Masaki, Yutaka Kuba, Daisuke Ueyama, Kouji Miyamoto, Yuuichiro Hayashi
  • Patent number: 9777394
    Abstract: A method of producing silicon single crystal ingot by pulling the silicon single crystal ingot made of an N-region by the CZ method, including: performing an EOSF inspection including a heat treatment to manifest oxide precipitates and selective etching on sample wafer from the silicon single crystal ingot composed of the N-region to measure a density of EOSF; performing a shallow-pit inspection to investigate a pattern of occurrence of a shallow pit; adjusting the pulling conditions according to result of identification of a defect region of the sample wafer by the EOSF and shallow-pit inspections to pull a next silicon single crystal ingot composed of the N-region, wherein in the identification of the defect region, for an N-region, what portion of an Nv-region or Ni-region the defect region corresponds to is also identified.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 3, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Susumu Sonokawa, Wataru Sato, Nobuaki Mitamura, Tomohiko Ohta
  • Patent number: 9766590
    Abstract: The method makes it possible to produce a decorated component for a timepiece or piece of jewellery. This component provided with the decoration may be, for example, a watch hand. To produce said component, a base substrate is used and a micromachining operation is performed on or in the base substrate to obtain an upper part of the component, which is provided with the decoration. The decoration is produced through the thickness of the upper part and in a programmed pattern. Thereafter, the upper part is placed on a luminescent or colored substance to obtain the component.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: September 19, 2017
    Assignee: Nivarox-FAR S.A.
    Inventor: Marc Stranczl
  • Patent number: 9766731
    Abstract: A method for manufacturing an edge-chamfered OGS touch panel is disclosed. Before a pre-prepared glass substrate is subjected to etching, an upper lamination film and a lower lamination film are respectively laminated on upper and lower surfaces of the glass substrate. The upper lamination film is smaller than the lower lamination film so that when the upper lamination film is laminated on the surface of the glass substrate, an edge exposure zone is preserved on the glass substrate at a location adjacent to a substrate edge. When the substrate edge of the glass substrate is subjected to etching, a chamfered edge is formed on the touch operation surface of the glass substrate that is adjacent to the substrate edge.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: September 19, 2017
    Assignee: Ghitron Technology Co., Ltd.
    Inventor: Chun-Yuan Lee
  • Patent number: 9767991
    Abstract: For a first period of time, a higher radiofrequency power is applied to generate a plasma in exposure to a substrate, while applying low bias voltage at the substrate level. For a second period of time, a lower radiofrequency power is applied to generate the plasma, while applying high bias voltage at the substrate level. The first and second periods of time are repeated in an alternating and successive manner for an overall period of time necessary to produce a desired effect on the substrate. In some embodiments, the first period of time is shorter than the second period of time such that on a time-averaged basis the plasma has a greater ion density than radical density. In some embodiments, the first period of time is greater than the second period of time such that on a time-averaged basis the plasma has a lower ion density than radical density.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: September 19, 2017
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Qian Fu, Ying Wu, Qing Xu