Abstract: Radio frequency (“RF”) absorbing devices used as RF termination devices or free space absorbers, for example, are formed with a planar wafer made of an inorganic thermally conductive material. The planar wafer has a first surface and a second surface opposite the first surface. A metallized resistive film is disposed on the first surface. A metallized reflective heat sink is disposed on the second surface.

Abstract: The present application provides a display panel including a light emitting layer and a touch layer; wherein the light emitting layer comprises a plurality of blue light emitting units, a plurality of green light emitting units, and a plurality of red light emitting units; wherein a top of the touch layer is provided with a transparent cover plate, the transparent cover plate is provided with a light enhancement region, and a projection of the light enhancement region on the light emitting layer covers the blue light emitting units.

Abstract: A fluid sensor includes a substrate having a top main surface region, wherein the top main surface region of the substrate forms a common system plane of the fluid sensor, a thermal radiation emitter on the top main surface region of the substrate, an optical filter structure on the top main surface region of the substrate, a waveguide on the main top surface region of the substrate, and a thermal radiation detector on the top main surface region of the substrate, wherein the thermal radiation detector provides a detector output signal based on a radiation strength of the filtered thermal radiation received from the waveguide.

Abstract: A semiconductor device may include a plurality of first contact structures, plug-shaped second contact structures configured to be connected to a first number of the plurality of first contact structures, respectively, a slit-shaped second contact structure configured to be connected to a second number of the plurality of first contact structures, adjacent in a first direction, and a third contact structure configured to be connected to sidewalls of the plug-shaped second contact structures, adjacent in the first direction.

Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm?3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm?3 or less.

Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of wiring line pairs each including a pair of first and second wiring lines extending in a first direction, a plurality of third wiring lines each extending in a second direction intersecting the first direction, and a plurality of memory cells provided between the wiring line pairs and the third wiring lines. Each of the memory cells includes a resistance change memory element connected to the third wiring line, and a switching element structure including a first switching element portion provided between the resistance change memory element and the first wiring line, and a second switching element portion provided between the resistance change memory element and the second wiring line.

Abstract: Techniques for fabricating a cored or coreless semiconductor package having one or more magnetic bilayer structures embedded therein are described. A magnetic bilayer structure includes a magnetic layer and a dielectric layer. For one technique, fabricating a cored or coreless semiconductor package includes: depositing a seed layer on a build-up layer; forming a raised pad structure and a trace on the seed layer; removing one or more uncovered portions of the seed layer to uncover top surfaces of one or more portions of the build-up layer; applying a magnetic bilayer structure on the raised pad structure, the trace, any unremoved portion of the seed layer, and the top surfaces of the one or more portions of the build-up layer, the magnetic bilayer structure comprises a magnetic layer and a dielectric layer; and forming a conductive structure on the raised pad structure. Other techniques are also described.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

Abstract: A bridge embedded interposer and a package substrate and a semiconductor package including the same includes: a connection structure including one or more redistribution layers, a first bridge disposed on the connection structure and including one or more first circuit layers electrically connected to the one or more redistribution layers, a frame disposed around the first bridge on the connection structure and including one or more wiring layers electrically connected to the one or more redistribution layers, and an encapsulant disposed on the connection structure and covering at least a portion of each of the first bridge and the frame.

Abstract: An optical semiconductor device includes a semiconductor light receiving element, a capacitor, and a carrier. The carrier has a mounting surface on which the semiconductor light receiving element and the capacitor are mounted. The optical semiconductor device includes a first conductive pattern including a first mounting area and a first bonding pad, a second conductive pattern including a second mounting area and a third mounting area, and a third conductive pattern including a second bonding pad. The first mounting area is connected to a first electrode of the semiconductor light receiving element. The second mounting area is connected to a second electrode of the semiconductor light receiving element. The third mounting area is connected to one electrode of the capacitor. The conductive patterns are separated from each other. The other electrode of the capacitor is electrically connected to the third conductive pattern via a wire.

Abstract: A semiconductor device, the device including: a first single crystal substrate and plurality of logic circuits, where the first single crystal substrate has a device area, where the device area is significantly larger than a reticle size, where the plurality of logic circuits include an array of processors, where the plurality of logic circuits include a first logic circuit, a second logic circuit, and third logic circuit, where the plurality of logic circuits include switching circuits to support replacing the first logic circuit and the second logic circuit by the third logic circuit; and a built-in-test-circuit (“BIST”), where the built-in-test-circuit is connected to test at least the first logic circuit and the second logic circuit.

Abstract: A semiconductor apparatus includes, a substrate having a main surface, an upper electrode disposed above the substrate, a first lower electrode and a second lower electrode disposed between the substrate and the upper electrode, an isolation region disposed between the first lower electrode and the second lower electrode, a functional layer configured to perform light emission or photoelectric conversion, and an interface layer disposed at least on the first lower electrode. The semiconductor apparatus further includes a first insulator portion that is disposed between the first lower electrode and the second lower electrode and includes a first portion disposed at a position farther away from the main surface than an upper surface of the interface layer.

Abstract: A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.

Abstract: A semiconductor memory device includes a capacitor on a substrate. The capacitor includes a first electrode, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. The second electrode includes a first layer, a second layer, and a third layer. The first layer is adjacent to the dielectric layer, and the third layer is spaced apart from the first layer with the second layer interposed therebetween. A concentration of nickel in the third layer is higher than a concentration of nickel in the first layer.

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are disclosed. The manufacturing method of the array substrate includes: providing a base substrate (200); forming a semiconductor layer on the base substrate; depositing an etch stop layer material on the semiconductor layer; subjecting the etch stop layer material to a wet etching process to form an etch stop layer; subjecting the semiconductor layer to a dry etching process to form an active layer, wherein the active layer includes a first region and a second region surrounding the first region, an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate.

Abstract: The present disclosure relates to a photodiode, a method for preparing the same, and an electronic device. The photodiode includes: a first electrode layer and a semiconductor structure that are stacked, a surface of the semiconductor structure away from the first electrode layer having a first concave-convex structure; and a second electrode layer arranged on a surface of the semiconductor structure away from the first electrode layer, a surface of the second electrode layer away from the first electrode layer having a second concave-convex structure.

Abstract: A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

Abstract: A method for measuring chips bonding strength includes steps as follows: An auxiliary pattern is formed on a first surface of a first chip. A second surface of a second chip is bonded to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, dimensions of the at least one gap space and the auxiliary pattern are measure respectively; and the bonding strength between the first chip and the second chip is estimated according to the dimensions.