Patents Examined by Duy T Nguyen
  • Substrate integrated inductors using high throughput additive deposition of hybrid magnetic materials
    Patent number: 11282800
    Abstract: An inductor in a device package and a method of forming the inductor in the device package are described. The inductor includes a first conductive layer disposed on a substrate. The inductor also has one or more hybrid magnetic additively manufactured (HMAM) layers disposed over and around the first conductive layer to form one or more via openings over the first conductive layer. The inductor further includes one or more vias disposed into the one or more via openings, wherein the one or more vias are only disposed on the portions of the exposed first conductive layer. The inductor has a dielectric layer disposed over and around the one or more vias, the HMAM layers, and the substrate. The inductor also has a second conductive layer disposed over the one or more vias and the dielectric layer.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Feras Eid, Georgios C. Dogiamis
  • Semiconductor memory device and method for manufacturing semiconductor memory device
    Patent number: 11276707
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body disposed in a first tier, the stacked body including a plurality of conductive layers stacked via an insulating layer; a first pillar that extends in the stacked body in a stacking direction of the stacked body; a first upper structure disposed in a second tier upper than the first tier; and a misalignment mark for inspecting misalignment between the first tier and the second tier, wherein the misalignment mark includes a second pillar that extends the first tier of the misalignment inspection region in the stacking direction, and a second upper structure disposed in the second tier of the misalignment inspection region and superposed on the second pillar in a top view.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 15, 2022
    Assignee: Kioxia Corporation
    Inventors: Yuichi Furuki, Hiroki Yamashita
  • Apparatus and method for forming alignment marks
    Patent number: 11270950
    Abstract: An apparatus and a method for forming alignment marks are disclosed. The method for forming alignment marks is a photolithography-free process and includes the following operations. A laser beam is provided. The laser beam is divided into a plurality of laser beams separated from each other. The plurality of laser beams is shaped into a plurality of patterned beams, so that the plurality of patterned beams is shaped with patterns corresponding to alignment marks. The plurality of patterned beams is projected onto a semiconductor wafer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chen Liu, Cheng-Hao Yu, Cheng-Yi Huang, Chao-Li Shih, Chih-Shen Yang
  • Semiconductor device using regions between pads
    Patent number: 11264495
    Abstract: A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: March 1, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tetsutaro Imagawa
  • Method of manufacturing power amplifier package embedded with input-output circuit
    Patent number: 11264251
    Abstract: A method of manufacturing a power amplifier package embedded with an input-output circuit including a dielectric circuit board, a heat sink and lead frames, the method comprising: the step of preparing the dielectric circuit board including the steps of forming a power amplifier hole in which a power amplifier chip is to be disposed on a dielectric substrate, printing an input matching network metal pattern on a left side of the power amplifier hole, and printing an output matching network metal pattern on a right side of the power amplifier hole, and sintering the input matching network metal pattern and the output matching network metal pattern printed on the dielectric substrate; the step of preparing the lead frames by etching alloy 42 and plating nickel; and the step of attaching the heat sink on a bottom surface of the dielectric circuit board.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 1, 2022
    Inventors: Sang-Hun Lee, Kue-Jin Han
  • Semiconductor storage device comprising staircase portion and method for manufacturing the same
    Patent number: 11264387
    Abstract: A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape. The staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, and at least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 1, 2022
    Assignee: Kioxia Corporation
    Inventors: Sota Matsumoto, Takahito Nishimura
  • Lens-free compound eye cameras based on angle-sensitive meta-surfaces
    Patent number: 11257856
    Abstract: A lens-free ultrathin imaging sensor using a compound-eye vision modality can be formed by forming a metasurface on each pixel of an array of pixels in a solid state imaging sensor. The metasurface can be configured to form a diffraction grating that directs light incident on the metasurface at a predefined angle to excite surface plasmon polaritons into the solid state imaging sensor and light incident at any other angle is reflected or diffracted away from the metasurface. Each pixel of the imaging sensor can be configured using the metasurface to only receive light incident from a different portion of a field of view. A computational imaging system can be used to construct the image from the individual pixels.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: February 22, 2022
    Assignee: TRUSTEES OF BOSTON UNIVERSITY
    Inventors: Roberto Paiella, Leonard Kogos
  • Radio frequency integrated circuit having relatively small circuit area and method of fabricating the same
    Patent number: 11257845
    Abstract: A radio frequency integrated circuit includes a silicon CMOS substrate with at least one CMOS device buried therein, and at least one thin film transistor formed on the silicon CMOS substrate and functioning as a radio frequency device. The thin film transistor includes a T-shaped gate electrode. A method for the fabricating a radio frequency integrated circuit is also disclosed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 22, 2022
    Assignee: National Chiao Tung University
    Inventors: Horng-Chih Lin, Yu-An Huang
  • Selective etch rate monitor
    Patent number: 11257698
    Abstract: Embodiments include a real time etch rate sensor and methods of for using a real time etch rate sensor. In an embodiment, the real time etch rate sensor includes a resonant system and a conductive housing. The resonant system may include a resonating body, a first electrode formed over a first surface of the resonating body, a second electrode formed over a second surface of the resonating body, and a sacrificial layer formed over the first electrode. In an embodiment, at least a portion of the first electrode is not covered by the sacrificial layer. In an embodiment, the conductive housing may secure the resonant system. Additionally, the conductive housing contacts the first electrode, and at least a portion of an interior edge of the conductive housing may be spaced away from the sacrificial layer.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: February 22, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Philip Allan Kraus, Timothy Joseph Franklin
  • Photosensor, display apparatus, and method of fabricating photosensor
    Patent number: 11251208
    Abstract: A photosensor includes a base substrate; an insulating layer on the base substrate; and a photodiode including a semiconductor junction on a side of the insulating layer away from the base substrate. The semiconductor junction includes a first polarity semiconductor layer, an intrinsic semiconductor layer, and a second polarity semiconductor layer, stacked on the insulating layer. The second polarity semiconductor layer encapsulates a lateral surface of the intrinsic semiconductor layer.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 15, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Chao Li, Jianhua Du, Feng Guan, Zhaohui Qiang, Zhi Wang, Yupeng Gao, Yang Lv
  • Semiconductor device structure with back-side layer to reduce leakage
    Patent number: 11244925
    Abstract: The present disclosure relates to a method of forming a semiconductor device structure. The method may be performed by forming a gate structure along a first side of a semiconductor substrate. The semiconductor substrate is thinned. Thinning the semiconductor substrate causes defects to form along a second side of the semiconductor substrate opposing the first side of the semiconductor substrate. Dopants are implanted into the second side of the semiconductor substrate after thinning the semiconductor substrate. The semiconductor substrate is annealed to form a doped layer after implanting the dopants. The doped layer is formed along the second side of the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Jeng-Shyan Lin, Hsun-Ying Huang
  • Array substrate combining sensing material with thin film transistor, method of fabricating same, and display panel including same
    Patent number: 11239262
    Abstract: An embodiment of the present invention discloses an array substrate, a method of fabricating the same, and a display panel. Compared with the conventional technology, the present invention combines a sensing material with thin film transistors to prepare a sensing layer on the thin film transistors, and since the thin film transistors can be formed by a large-area preparation, the sensors can be formed by a large-area preparation accordingly, thereby improving a performance of the sensors and reducing the production cost of the sensors.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: February 1, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Juncheng Xiao, Chao Tian
  • Battery-free and substrate-free IoT and AI system package
    Patent number: 11239150
    Abstract: A tetherless system-in-package includes a first integrated circuit (IC) chip having interconnects and energy harvesting elements. A super-capacitor is configured to store a charge output by the energy harvesting elements. At least a second IC chipset including a smart chip and an optical I/O or an RF I/O is aligned and bonded to at least one of the interconnects of the first IC chip. The first IC chip and the second IC chip are configured to receive a portion of the charge stored by the super-capacitor.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: February 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frank Robert Libsch, Stephen W. Bedell, Ning Li
  • Semiconductor wafers and semiconductor devices with barrier layer and methods of manufacturing
    Patent number: 11239384
    Abstract: A semiconductor ingot is sliced to obtain a semiconductor slice with a front side surface and a rear side surface parallel to the front side surface. A passivation layer is formed directly on at least one of the front side surface and the rear side surface. A barrier layer including least one of silicon carbide, a ternary nitride, and a ternary carbide is formed on the rear side surface.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: February 1, 2022
    Assignee: INFINEON TECHNOLOGIESAG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Spin-torque transfer switchable magnetic tunnel junction unit and a memory device
    Patent number: 11227645
    Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: January 18, 2022
    Assignee: IMEC VZW
    Inventors: Sushil Sakhare, Manu Komalan Perumkunnil, Johan Swerts, Gouri Sankar Kar, Trong Huynh Bao
  • Method of manufacturing photomask set for forming patterns, and method of manufacturing semiconductor device using the photomask set
    Patent number: 11226552
    Abstract: A method of manufacturing a photomask set includes: preparing a mask layout, the mask layout including a plurality of first layout patterns apart from one another in a first region, wherein distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, in which a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout pattern into at least two mask layouts; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in each of the mask layout patterns split into at least two mask layouts.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hungbae Ahn, Sangoh Park, Sunggon Jung
  • Semiconductor device having chip stacked and molded
    Patent number: 11227826
    Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 18, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Tajima, Kazuo Shimokawa
  • Determining device operability via metal-induced layer exchange
    Patent number: 11221359
    Abstract: Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Kangguo Cheng
  • Multi-axis movement for transfer of semiconductor devices
    Patent number: 11217471
    Abstract: A method for executing a direct transfer of semiconductor device die from a first substrate to transfer locations on a second substrate. The method includes determining a position of impact wires disposed on a transfer head, semiconductor device die, and transfer locations; determining whether there are at least two positions that an impact wire, a semiconductor device die, and a transfer locations are aligned within a threshold tolerance; and transferring, by the impact wires, the semiconductor device die such that the semiconductor device die detaches from the first substrate and attaches to transfer locations on the second substrate. The transferring being completed based at least in part on determining that the impact wire, the semiconductor device die, and the circuit trace are aligned within the threshold tolerance.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 4, 2022
    Assignee: Rohinni, LLC
    Inventors: Cody Peterson, Andrew Huska
  • 3D semiconductor device and structure with multiple isolation layers
    Patent number: 11217472
    Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, where the bonded includes at least one oxide to oxide bond, and where the bonded includes at least one metal to metal bond.
    Type: Grant
    Filed: April 18, 2021
    Date of Patent: January 4, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar