Patents Examined by Duy T Nguyen
  • Structure for capacitor protection, package structure, and method of forming package structure
    Patent number: 11450732
    Abstract: A package structure includes: a substrate; a chip arranged on a part of a surface of the substrate; a metal thermal conducting layer arranged on a top surface of the chip; a capacitive structure arranged on another part of the surface of the substrate and arranged to be independent from the chip; and a cover including a first cover layer and a second cover layer connected to the first cover layer. A first opening is defined to extend through the first and the second cover layers. The second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer. The first cover layer is arranged on the capacitive structure. The chip is received in the first opening. The second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 20, 2022
    Assignee: SUZHOU TF-AMD SEMICONDUCTOR CO. LTD.
    Inventors: Zhe Liu, Borrong Huang, Hongjie Wang, Diong Hing Ding
  • Electronic device
    Patent number: 11442515
    Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 13, 2022
    Assignee: JAPAN DISPLAY INC.
    Inventors: Akihiro Hanada, Hajime Watakabe, Kazufumi Watabe
  • Self-aligned gate endcap (SAGE) architecture having gate or contact plugs
    Patent number: 11444171
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez
  • Electronic devices having a sensor and a translucent mold compound and methods of manufacturing electronic devices
    Patent number: 11437526
    Abstract: In one example, an electronic device includes: an electronic component comprising a sensor and an electrical interconnect; a substrate comprising an electrically conductive material and a translucent mold compound, wherein the electrically conductive material is coupled to the translucent mold compound and wherein the electrical interconnect of the electronic component is coupled to the electrically conductive material of the substrate; and a translucent underfill contacting the electrical interconnect and between the translucent mold compound and the sensor. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: September 6, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Ji Young Chung, Sung Hwan Yang, Jae Ho Lee
  • Process and structures for fabrication of solar cells
    Patent number: 11437528
    Abstract: Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Use of a laser to form the contact holes is facilitated by replacing films formed on the diffusion regions with a film that has substantially uniform thickness. Contact holes may be formed to deep diffusion regions to increase the laser ablation process margins. The laser configuration may be tailored to form contact holes through dielectric films of varying thicknesses.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 6, 2022
    Assignee: SunPower Corporation
    Inventors: Gabriel Harley, David D. Smith, Tim Dennis, Ann Waldhauer, Taeseok Kim, Peter John Cousins
  • Method of manufacturing metal nitride film and electronic device including metal nitride film
    Patent number: 11424317
    Abstract: A capacitor includes: a lower electrode including a metal nitride represented by MM?N, wherein M is a metal element, M? is an element different from M, and N is nitrogen; a dielectric layer on the lower electrode; an interfacial layer between the lower electrode and the dielectric layer and including a metal nitrate represented by MM?ON, wherein M is a metal element, M? is an element different from M, N is nitrogen, and O is oxygen; and an upper electrode on the dielectric layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: August 23, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeonggyu Song, Kyooho Jung, Younsoo Kim, Haeryong Kim, Jooho Lee
  • Semiconductor structure having a semiconducture substrate and an isolation component
    Patent number: 11417647
    Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: August 16, 2022
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Yicheng Du, Meng Wang, Hui Yu
  • Vertical transistors with channel region having vertically elongated crystal grains that individually are directly against both of the top and bottom source/drain regions
    Patent number: 11417730
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Vassil N. Antonov, Kamal M. Karda, Michael Mutch, Hung-Wei Liu, Jeffery B. Hull
  • Optimized weight heat spreader for an electronic package
    Patent number: 11410905
    Abstract: A heat spreader is disclosed with regions where material is absent to reduce the mass/weight of the heat spreader without substantially reducing the temperature of the semiconductor chip and without substantially affecting the warpage and mechanical stress/strain in the electronic package.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Kamal K. Sikka, Kenneth Marston, Tuhin Sinha, Shidong Li
  • Electronic device with die pad and leads, and method of manufacturing
    Patent number: 11404356
    Abstract: An electronic device includes an electronic component provided with a first electrode pad, a die pad including an obverse surface facing in a first direction with the electronic component mounted on the obverse surface, a first lead, a second lead, and a first connection member electrically connecting the first electrode pad and the first lead to each other. The first lead and the second lead are disposed, as viewed in the first direction, on a same side of the die pad in a second direction perpendicular to the first direction. The first lead includes a first pad portion and a first extended portion. The first connection member is bonded to the first pad portion. The first extended portion extends from the first pad portion up to a position located between the die pad and the second lead as viewed in the first direction.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 2, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Katsutoki Shirai, Yoshio Higashida
  • Method for transferring a useful layer into a supporting substrate
    Patent number: 11401162
    Abstract: A process for transferring a useful layer to a carrier substrate including a first surface is provided, the process including the steps of: providing a donor substrate including a first surface, a weakened zone including implanted species, the useful layer, which is bounded by the weakened zone and by the first surface of the donor substrate, and an amorphous zone disposed, in the useful layer, parallel to the weakened zone; assembling, on a side of the first surface of the donor substrate and on a side of the first surface of the carrier substrate, the donor substrate with the carrier substrate by bonding, such that the amorphous zone is at least partially facing at least one cavity that is partially bounded by the first surface of the donor substrate; and splitting the donor substrate along the weakened zone so as to reveal the useful layer.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 2, 2022
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Lamine Benaissa, Thierry Salvetat
  • Display panel where opening rates of first and second subpixels are less than that of a third subpixel while channel ratios of the first and second subpixels are greater than that of the third subpixel and display apparatus
    Patent number: 11404509
    Abstract: The present application discloses a display panel and a display apparatus. The display panel includes a plurality of pixels. Each of the pixels at least includes a first sub pixel, a second sub pixel and a third sub pixel corresponding to blue. The first sub pixel includes a first active switch. The second sub pixel includes a second active switch. The third sub pixel includes a third active switch. The opening rates of the first sub pixel and the second sub pixel are less than the opening rate of the third sub pixel. The channel ratios of the first active switch and the second active switch are greater than the channel ratio of the third active switch.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 2, 2022
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chuan Wu
  • Memory device having multiple chips and method for manufacturing the same
    Patent number: 11387227
    Abstract: According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 12, 2022
    Assignee: Kioxia Corporation
    Inventor: Mutsumi Okajima
  • Semiconductor device manufacturing method
    Patent number: 11380585
    Abstract: A semiconductor device manufacturing method includes thinning a wafer to form a wafer having an annular protruding portion on a peripheral portion thereof by grinding a central portion of a back surface of the wafer and then performing wet etching on the back surface of the wafer, forming a backside electrode on the back surface of the wafer, performing plating to evenly form a metal film on a portion of the backside electrode on the annular protruding portion, attaching a dicing tape to the metal film, and dicing the wafer having the dicing tape attached thereto.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 5, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryuji Ueno, Masatoshi Sunamoto
  • Magnetic memory cell having deterministic switching and high data retention
    Patent number: 11380839
    Abstract: A magnetic memory (MRAM) cell, comprising: a first layer formed from a substantially electrically conductive material; and a magnetic tunnel junction (MTJ) stack formed over the first layer, wherein the MTJ stack comprises: a ferromagnetic reference layer having an in-plane reference magnetization; a tunnel barrier layer; and a ferromagnetic storage layer between the tunnel barrier layer and the first layer, the storage layer having an in-plane storage magnetization; wherein the MTJ stack comprises an arrangement for providing an in-plane uniaxial anisotropy in the storage layer; wherein said in-plane uniaxial anisotropy makes an angle with the direction of the write current that is between 5° and 90°, and wherein said in-plane uniaxial anisotropy has an energy between 40 and 200 kBT and wherein coercivity is larger than 200 Oe.
    Type: Grant
    Filed: May 2, 2020
    Date of Patent: July 5, 2022
    Assignees: Antaios, Centre National De La Recherche Scientifique
    Inventors: Witold Kula, Marc Drouard, Gilles Gaudin, Jean-Pierre Nozieres
  • Flash with shallow trench in channel region and method for manufacturing the same
    Patent number: 11374014
    Abstract: The present invention discloses a flash. A channel region comprises a first shallow trench formed in the surface area of a semiconductor substrate. A tunneling dielectric layer and a polysilicon floating gate are formed in the first shallow trench and extended to the outside of the first shallow trench. A control dielectric layer and a polysilicon control gate are sequentially formed on the two side surfaces in the width direction and the top surface of the polysilicon floating gate. A source region and a drain region are formed in a self-aligned manner in active regions on the two sides in the length direction of the polysilicon floating gate. The present invention further discloses a method for manufacturing a flash. The present invention can break through the limitation of the length of the channel on the size of the memory cell, thus reducing the area of the memory cell.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 28, 2022
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Chengcheng Wang, Rong Zou, Qiwei Wang
  • Chip on film and display device
    Patent number: 11355425
    Abstract: The present disclosure relates to a chip on film and a display device. The chip on film includes a body and an insulating protective film arranged on the body, in which the body includes a first area, a first binding area for binding and connecting to the back surface of the display panel, and a first bendable area located between the first area and the first binding area and capable of being bent in a first direction; and the insulating protection film includes a first connection area connected to the first area, a second connection area for connecting to the back surface of the display panel, and a second bendable area located between the first connection area and the second connection area and capable of being bent in a second direction opposite to the first direction.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: June 7, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kaiwen Wang, Mookeun Shin, Xiaojun Wu, Xuanxuan Qiao, Aixia Sang, Qiang Zhang, Zhenyu Han
  • Integrated circuit in hybrid row height structure
    Patent number: 11355395
    Abstract: A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang, Tzu-Ying Lin
  • Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
    Patent number: 11355380
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and on the first level, where the control circuits include first single crystal transistors, where the control circuits include at least two metal layers; forming at least one second level disposed on top of the first level; performing a first etch step within the second level; forming at least one third level disposed on top of the at least one second level; performing a second etch step within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the first memory cells include second transistors, and where the second memory cells include third transistors.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 7, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Enhancement of yield of functional microelectronic devices
    Patent number: 11346882
    Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: May 31, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Carlos A. Fonseca, Nathan Ip, Joel Estrella