Patents Examined by Duy-Vu Deo
  • Patent number: 9708731
    Abstract: A method of producing a silicon single crystal is provided. The method may include taking a real image of a heat shield including a circular opening and a mirror image of the heat shield reflected on a surface of the silicon melt, measuring a spacing between the real image and the mirror image, calculating a position of the surface of the silicon melt, taking an image of a bright zone that appears in a vicinity of an interface between the silicon melt and the silicon single crystal, calculating a position of the surface of the silicon melt based on a center position of the silicon single crystal determined from the image of the bright zone, and controlling the position of the surface of the silicon melt during a pulling of the silicon single crystal while referring to data of the calculated positions of the surface of the silicon melt.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 18, 2017
    Assignee: SUMCO CORPORATION
    Inventors: Keiichi Takanashi, Ken Hamada
  • Patent number: 8747689
    Abstract: There are provided a liquid processing method and a liquid processing apparatus capable of providing a high etching rate and a high etching selectivity for silicon nitride against silicon oxide, and a storage medium storing the method thereon. In the method for etching, by an etching solution, a substrate on which silicon nitride and silicon oxide are exposed, the etching solution is produced by mixing a fluorine ion source material, water and a boiling point adjusting agent; the produced etching solution is heated to a substrate processing temperature equal to or higher than 140° C.; after a temperature of the etching solution reaches the substrate processing temperature, the temperature of the etching solution is maintained at the substrate processing temperature for a first preset time; and after a lapse of the first preset time, the substrate is etched by the etching solution maintained at the substrate processing temperature.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: June 10, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiroki Ohno, Takehiko Orii
  • Patent number: 8734658
    Abstract: A resist film is formed on a cold-rolled steel sheet so as to fabricate a groove by etching. At this point, a steel sheet exposed portion where a portion of the steel sheet is exposed is formed in the resist film, and the steel sheet exposed portion has a first region oriented in a sheet width direction, and a plurality of second regions starting from the first region, widths of the first region and the second regions being 20 ?m to 100 ?m, and a distance from an end portion of one of the second regions to an end portion of another of the second regions adjacent thereto being 60 ?m to 570 ?m.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: May 27, 2014
    Assignee: Nippon Steel & Sumitomo Metal Corporation
    Inventors: Keiji Iwata, Yasuhiro Kikuchi
  • Patent number: 8070970
    Abstract: A layer of photoresist is spread on a metal substrate and heated, this layer is exposed through a mask to UV irradiation, the parts not photocured are developed, by dissolving them, so as to obtain a mold, a first layer of metal or of an alloy is galvanically deposited in the open parts of the mold, the metal structure and the mold are leveled by machining so as to obtain a plane upper surface, a metal ply layer is deposited on the entire upper surface, and then the above steps are repeated. A second layer of metal or an alloy is galvanically deposited in the open parts of the mold, the multilayer metal structure obtained is detached from the substrate by delamination and the photoresist is cured, the photoresist is separated so as to free the multilayer metal structure, and then that portion of the metal ply layer or layers which is not inserted between two electrodeposited metal layers is removed.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: December 6, 2011
    Assignee: Doniar SA
    Inventor: Clement Saucy
  • Patent number: 7601643
    Abstract: An arrangement and method for fabricating a semiconductor wafer which utilizes a nonaqueous solvent rinse is disclosed.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: October 13, 2009
    Assignee: LSI Logic Corporation
    Inventor: Charles E. May
  • Patent number: 7521083
    Abstract: Method and apparatus for treatment of a surface of a rotor blade of a windmill, the apparatus being placed in such a manner to be moveable in relation to the surface of a rotor blade, and the apparatus being caused to move depending on a form of treatment determined by means for treatment mounted on, in or next to the apparatus. In this manner, various forms of treatment of a rotor blade may be carried out such as for instance washing, finishing, sealing, etc.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: April 21, 2009
    Assignee: PP Energy APS
    Inventor: Paul Teichert
  • Patent number: 7517564
    Abstract: The invention is directed to a method by exposing at least a portion of a luminescent coating disposed on a surface of an article to ultraviolet light at one or more preselected wavelengths causing said luminescent coating to exhibit a luminescence spectrum, the luminescence spectrum exhibiting a plurality of intensity peaks that have been predetermined to create a standard; determining the intensity of at least two peaks in the luminescence spectrum of the coating; determining a peak intensity ratio of the at least two peaks; comparing the peak intensity ratio determined with the standard; and, classifying the article according to whether or not the peak intensity ratio does or does not match the standard; wherein the luminescent coating is a particulate luminescent composition comprising a rare earth doped fluoride represented by the chemical formula REx(CaaSrbBac)1?xF2+x?2yOy wherein RE represents a three-valent rare-earth element, 0.005?x?0.20, and 0?y?0.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: April 14, 2009
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Michael Karl Crawford, Kurt Richard Mikeska
  • Patent number: 7501346
    Abstract: The invention provides a chemical-mechanical polishing composition comprising silica, a compound in an amount sufficient to provide about 0.2 mM to about 10 mM of a metal cation selected from the group consisting of gallium (III), chromium (II), and chromium (III), and water, wherein the polishing composition has a pH of about 1 to about 6. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: March 10, 2009
    Assignee: Cabot Microelectronics Corporation
    Inventor: Steven K. Grumbine
  • Patent number: 7494594
    Abstract: An electrostatic actuator for increasing a swing (deflection angle) of a movable structure includes a laminate substrate in which a thin film silicon layer is formed on a silicon substrate through a buried insulating film and a torsion beam movable structure constructed with the thin film silicon layer. A potential difference is generated between a movable side comb-tooth electrode of the movable structure and a fixed side comb-tooth electrode disposed to face the movable side comb-tooth electrode to swing the movable structure. The fixed side comb-tooth electrode is formed in the inside of a through hole bored through the laminate substrate.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 24, 2009
    Assignee: DENSO CORPORATION
    Inventors: Kunihiro Onoda, Hideaki Nishikawa, Tetsuo Yoshioka
  • Patent number: 7468319
    Abstract: The present invention relates to a method for preventing a metal corrosion in a semiconductor device. The present method includes the steps of etching of a metal layer in a chamber, the metal layer having a photoresist pattern thereon or thereover; oxidizing a surface of the metal layer using a plasma comprising N2O in the same chamber; and removing the photoresist. Therefore, metal corrosion as well as bridges between metal wirings can be suppressed or prevented, thereby improving the profile of metal layer and the reliability and yield of the semiconductor device.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: December 23, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jae Suk Lee
  • Patent number: 7459097
    Abstract: A method of forming a conductive pattern can form a conductive pattern where the aspect ratio of the height to the width is high with favorable electrical connectivity.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: December 2, 2008
    Assignee: Fujitsu Limited
    Inventors: Kotaro Yamazaki, Takashi Ito, Junji Sato
  • Patent number: 7455785
    Abstract: A flatness of a substrate is determined to achieve a desired flatness of a mask blank by predicting the variation in flatness resulting from a film stress of a thin film formed on the substrate. The flatness is adjusted by measuring the flatness of the substrate as a measured flatness, selecting a load type with reference to the measured flatness, and polishing the substrate under pressure distribution specified by the load type. A principal surface of the substrate has a flatness greater than 0 ?m and not greater than 0.25 ?m. A polishing apparatus includes a rotatable surface table, a polishing pad formed thereon, abrasive supplying means for supplying an abrasive to the polishing pad, substrate holding means, and substrate pressing means for pressing the substrate. The substrate pressing means has a plurality of pressing members for individually and desirably pressing a plurality of divided regions of the substrate surface.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: November 25, 2008
    Assignee: Hoya Corporation
    Inventors: Kesahiro Koike, Masato Ohtsuka, Yasutaka Tochihara
  • Patent number: 7416676
    Abstract: A plasma etching method for etching an etching target layer of a silicon layer through a mask of a silicon oxide film includes the following sequential steps of forming an opening in the silicon oxide film, wherein an opening dimension of a portion between a top and a bottom surface of the mask is enlarged compared to opening dimensions of the top and the bottom surface of the mask and etching the silicon layer by using a halogen containing gas. A gaseous mixture containing HBr gas, NF3 gas and O2 gas is used as the halogen containing gas. A hole or a trench having an opening diameter or an opening width equal to or smaller than 0.2 ?m is formed in the etching target layer. Further, a hole or a trench having an aspect ratio equal to or greater than forty is formed in the etching target layer.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: August 26, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Jin Fujihara, Katsumi Horiguchi
  • Patent number: 7413990
    Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: August 19, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Yan Ye, Xiaoye Zhao, Hong Du
  • Patent number: 7407596
    Abstract: A fluxgate sensor is integrated in a printed circuit board. The fluxgate sensor has two bar-type (or rectangular-ring shaped) soft magnetic cores to form a closed magnetic path on a printed circuit board and an excitation coil in the form of a metal film is wound around the two bar-type soft magnetic cores either in a united structure that winds the two bar-type soft magnetic cores altogether, or in a separated structure that winds the two bar-type soft magnetic cores respectively, both in a pattern of number ‘8’. A pick-up coil is mounted on the excitation coil, either winding the two bars altogether, or respectively, in a solenoid pattern. The fluxgate sensor integrated in the printed circuit board can be mass-produced at a cheap manufacturing cost. The fluxgate sensor also can be made compact-sized, and at the same time, is capable of forming a closed-magnetic path.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: August 5, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Won-youl Choi, Byeong-cheon Koh, Kyung-won Na, Sang-on Choi, Myung-sam Kang, Keon-yang Park
  • Patent number: 7405164
    Abstract: In an apparatus and method for removing a photoresist structure from a substrate, a chamber for receiving the substrate includes a showerhead for uniformly distributing a mixture of water vapor and ozone gas onto the substrate. The showerhead includes a first space having walls and configured to receive the water vapor, and a second space connected to the first space so that the water vapor is supplied to and partially condensed into liquid water on one or more walls of the first space. Ozone gas and water vapor without liquid water may be supplied to the second space to form the mixture therein. The showerhead may be heated to vaporize the liquid water on a given surface of the first space.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: July 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Gi Kim, In-Seak Hwang, Dae-Hyuk Chung, Kyoung-Hwan Kim
  • Patent number: 7402525
    Abstract: A gate electrode is formed of a laminate structure comprising a plurality of conductive layers such that the width along the channel of a lower first conductive layer is larger than that of an upper second conductive layer The gate electrode is used as a mask during ion doping for forming an LDD. A mask pattern for forming the gate electrode is processed into an optimum shape in combination with dry etching so that the LDD overlapping with the gate electrode(Lov) is 1 ?m or more, and preferably, 1.5 ?m or more.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 22, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shigeharu Monoe
  • Patent number: 7399421
    Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobowitz, Stephen L. Buchwalter, Casimer DeCusatis, Peter A. Gruber, Da-Yuan Shih
  • Patent number: 7396476
    Abstract: Methods of fabricating comb drive devices utilizing one or more sacrificial etch-buffers are disclosed. An illustrative fabrication method may include the steps of etching a pattern onto a wafer substrate defining one or more comb drive elements and sacrificial etch-buffers, liberating and removing one or more sacrificial etch-buffers prior to wafer bonding, bonding the etched wafer substrate to an underlying support substrate, and etching away the wafer substrate. In some embodiments, the sacrificial etch-buffers are removed after bonding the wafer to the support substrate. The sacrificial etch-buffers can be provided at one or more selective regions to provide greater uniformity in etch rate during etching. A comb drive device in accordance with an illustrative embodiment can include a number of interdigitated comb fingers each having a more uniform profile along their length and/or at their ends, producing less harmonic distortion during operation.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: July 8, 2008
    Assignee: Honeywell International Inc.
    Inventors: Jeffrey A. Ridley, James A. Neus
  • Patent number: 7393788
    Abstract: A method and system for selectively and uniformly etching a dielectric layer with respect to silicon and polysilicon in a dry plasma etching system are described. The etch chemistry comprises the use of fluorohydrocarbons, such as CH2F2 and CHF3. High etch selectivity and acceptable uniformity can be achieved by selecting a process condition, including the flow rate of CH2F2 and the power coupled to the dry plasma etching system, such that a proper balance of active etching radicals and polymer forming radicals are formed within the etching plasma.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: July 1, 2008
    Inventor: Julie A. Cook