Abstract: A full-image exposure process of a field of a semiconductor wafer having an alignment mark is disclosed. The field of the semiconductor wafer may be located at an edge of the wafer, such as the lower-left or upper-right edge of the wafer, and is exposed using a full-image mask, such as a positive photoresist mask, and that can be inclusive of the alignment mark. A clear out process is subsequently performed around the alignment mark on the field of the semiconductor wafer to reveal the alignment mark. Prior deposition of photoresist or other layers, and subsequent exposure and stripping of the photoresist and etching of the other layers may also be performed.

Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

Abstract: A method of anisotropic etching of structures in a semiconductor body, in particular of recesses in a silicon body (18) exactly defined laterally by an etching mask, by using a plasma (28) is proposed. An ion acceleration voltage induced in particular by a high-frequency AC voltage is applied to the semiconductor body at least during an etching step having a predefined duration. The duration of the etching step is further subdivided into at least two etching segments between which the ion acceleration voltage applied is modified each time. Preferably two etching segments are provided, a higher acceleration voltage being used during the first etching segment than during the second etching step. The length of the first etching segment can furthermore be determined dynamically or statically during the etching steps using a device for the detection of a polymer breakdown.

Abstract: A composition and a method for planarizing or polishing a surface with the composition are provided. The composition comprises a liquid carrier, a chemical accelerator, and solids comprising about 5-90 wt. % of fumed metal oxide, and about 10-95 wt. % of abrasive particles, wherein about 90% or more of the abrasive particles (by number) have a particle size no greater than 100 nm. The composition of the present invention is useful in planarizing or polishing a surface with high polishing efficiency, uniformity, and removal rate, with minimal defectivity, such as field loss of underlying structures and topography.

Abstract: A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysilicon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increase surface area as a result of the formation of the lateral grooves.

Abstract: A method is provided whereby successive layers of bond pads can be created. A pattern is created in the preceding level of metal bond pad, a dielectric is deposited over this pattern, openings are created in the dielectric that match the pattern, an opening is created above this pattern and metal is deposited inside this opening creating a square metal bond pad that is joined to the pattern that has been created in the metal of the preceding bond pad.

Abstract: A method for forming within a dielectric layer upon a substrate within a microelectronics fabrication a series of contact via holes etched through the dielectric layer to multi-level contact layers employing reactive plasma etching methods to form the series of contact via holes. The first plasma etch method employs fluorine containing gases to form the etched via holes, and then the second plasma etch method employs oxygen and a fluorocarbon gas to complete the etching of the via holes and remove residual materials. The etched via holes access multi-level contact layers formed upon the substrate at differing heights with respect to the substrate, penetrating through at least one contact layer. This permits formation of a series of electrical contacts, between the series of contact layers and patterned conductor layers through the series of via holes, with low electrical resistances.

Abstract: A chemical mechanical polishing composition comprising a soluble cerium compound at a pH above 3 and a method to selectively polish a silicon oxide overfill in preference to a silicon nitride film layer in a single step during the manufacture of integrated circuits and semiconductors.

Abstract: A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP.

Abstract: A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern are partially etched by a sputtering etch technology. In this etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.

Abstract: A method for processing a silicon substrate disposed in a substrate process chamber includes transferring the substrate into the substrate process chamber. The substrate having a hard mask formed thereon and a patterned photoresist overlying the hard mask to expose portions of the hard mask. The chamber being the type having a source power system and a bias power system. The method further includes etching the exposed portions of the hard mask to expose portions of the silicon substrate underlying the hard mask. Thereafter, the patterned photoresist is exposed to a first plasma formed from a first process gas to remove the photoresist from the hard mask. Thereafter, the exposed silicon substrate is etched by exposing the substrate to a second plasma formed from a second process gas by applying RF energy from the source power system and biasing the plasma toward the substrate. The substrate is transferred out of the substrate processing chamber.

Abstract: Methods for etching or removing oxide scale from a substrate by applying a composition containing a polymer and an effective amount of hydrofluoric acid and maintaining the composition on the substrate until the substrate is etched or the oxide scale is removed.

Abstract: A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.

Abstract: A new method for forming a high quality cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A thermal oxide layer is grown overlying the semiconductor substrate. A titanium layer is deposited overlying the thermal oxide layer. A cobalt layer is deposited overlying the titanium layer. A titanium nitride capping layer is deposited over the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. The substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide to complete formation of a cobalt disilicide film in the manufacture of an integrated circuit.

Abstract: In a processing chamber of an etching apparatus a lower electrode and an upper electrode grounded through a processing container are disposed oppositely to each other. A first high frequency power supply section composed of a first filter, a first matching device, and a first power source, and a second high frequency power supply section composed of a second filter, a second matching device, and a second power source are connected to the lower electrode. A superimposed power of two frequencies composed of a first high frequency power component of at least 10 MHz produced from the first power source and a second high frequency power component of at least 2 MHz produced from the second power source is applied to the lower electrode. Ions in the plasma do not accelerated by changes of electric field in the processing chamber, but are accelerated by a self-bias voltage and collide only against a wafer on the lower electrode.

Abstract: A method for forming a top interconnection level and bonding pads for an integrated circuit chip is described. The interconnection level is formed by a damascene type process. Bonding pads are placed above the plane of the wiring channels of the interconnection level. This eliminates the problem of dishing of the relatively large bonding pads which occurs, during chemical mechanical polishing, when the bonding pads are on the same level as the interconnection metallurgy. The interconnection wiring includes a smaller pad base segment upon which the larger bonding pad is then formed. The bonding pad base segments are small enough that dishing during CMP is not a problem. Placing the bonding pads on pad bases provides for a more robust pad. The top level and bonding pad fabrication procedures are applicable with various conductive materials including aluminum, tungsten, and copper.

Abstract: A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.

Abstract: Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.

Abstract: A process for manufacturing a semiconductor substrate, comprising the step of preparing a first substrate which has a surface layer portion subjected to hydrogen annealing, the separation-layer formation step of implanting ions of hydrogen or the like into the first substrate from the side of the surface layer portion, thereby to form a separation layer, the adhesion step of bonding the first substrate and a second substrate to each other so that the surface layer portion may lie inside, thereby to form a multilayer structure, and the transfer step of separating the multilayer structure by utilizing the separation layer, thereby to transfer the less-defective layer of the surface layer portion onto the second substrate. The less-defective layer is a single-crystal silicon layer in which defects inherent in a bulk wafer, such as COPs and FPDs, are decreased.

Abstract: A method for fabricating a semiconductor device of the present invention comprises the steps of: a) depositing a masking film on a first compound semiconductor layer formed on a semiconductor substrate; b) patterning the masking film so that the film has an opening; c) etching away at least an uppermost part of the first semiconductor layer, which part is located inside the opening and includes a degraded layer formed in the step a) or b), using a first etchant and the masking film; and d) patterning the first semiconductor layer by etching away another part of the first layer using a second etchant and the masking film. That another part is located inside the opening and does not include the uppermost part with the degraded layer. The second etchant allows for etching the first layer at a rate lower than a rate realized by the first etchant.