Abstract: Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.

Abstract: A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.

Abstract: A method of forming a trench isolation in a semiconductor substrate is described, which comprises the steps of forming a trench on the substrate, forming a diffusion barrier insulating layer, forming a thermal oxide layer both sidewall and bottom of the trench contacted with the diffusion barrier insulating layer, forming a nitride liner, and forming trench isolation material to fill the trench. A multi-structure of the barrier layer and the thermal oxide layer is provided between the nitride liner and the trench, resulting in minimization of transistor characteristic deterioration. A thin thermal oxide layer is formed to achieve improved trench etching profile.

Abstract: In a process for manufacturing deep trench (32) memory cells, a method of enhancing the process window by better protecting the nitride spacer (52) prior to the process of stripping the pad nitride layer (38). The method also provides for the deposition of a nitride liner (64) and offers an additional advantage of not requiring the top shoulder (58) of the nitride spacer (52) to be over etched during its formation.

Abstract: A method for fabricating an Al—Si—containing alloy line, which is adapted to form a conductive line on a substrate, is described. A first conductive layer, a second conductive layer and an Al—Si—containing alloy layer are sequentially formed on the substrate. Then, the substrate temperature is rapidly lowered to between about 0° C. and 25° C. in about 1 second to 10 seconds. A patterned photo-resist layer is formed on the third conductive layer. The patterned photo-resist layer is used as a mask, and the third conductive layer, the Al—Si—containing alloy layer, the second conductive layer and the first conductive layer are etched to form the conductive line.

Abstract: A method of through-etching a substrate that is simplified and by which the flow of ions can be kept to be regular during a plasma dry etching process, is provided. According to this method, a buffer layer is formed on a first plane of the substrate, a metal layer is formed on the buffer layer, an etching mask pattern is formed on a second plane opposite to the first plane, and the substrate is through-etched with the etching mask pattern as an etching mask. Preferably, the substrate is formed of a single-crystal silicon, the buffer layer is formed of silicon dioxide, and the metal layer is formed of aluminum.

Abstract: A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.

Abstract: A plasma etching method for etching a sample within an etching chamber having a sidewall, an exchangeable jacket which is held inside of the sidewall, and a heating mechanism proximate to top end of the exchangeable jacket for generating heat which radiates towards an inside of the etching chamber. The plasma etching method further including a step of evacuating the etching chamber by an evacuation system, a step of supplying an etching gas into the etching chamber, a step of generating a plasma for performing etching of the sample in the etching chamber, and a step of conducting a heating operation by the heating mechanism during an initial stage of the step of generating a plasma.

Abstract: A method of providing a microprojection (180) on the surface of a first material, the microprojection having a base portion adjacent the first material and a remote, or a tip portion, and a duct (182) at least in a region of the tip portion and the method comprising micro-machining the first material to provide the micro-projection duct. Various uses of the microprojection are also disclosed including light guides and cuvettes from micro-analytical systems, microneedles for transdermal fluid delivery or the like.

Abstract: A nanomachining method for producing high-aspect ratio precise nanostructures. The method begins by irradiating a wafer with an energetic charged-particle beam. Next, a layer of patterning material is deposited on one side of the wafer and a layer of etch stop or metal plating base is coated on the other side of the wafer. A desired pattern is generated in the patterning material on the top surface of the irradiated wafer using conventional electron-beam lithography techniques. Lastly, the wafer is placed in an appropriate chemical solution that produces a directional etch of the wafer only in the area from which the resist has been removed by the patterning process. The high mechanical strength of the wafer materials compared to the organic resists used in conventional lithography techniques with allows the transfer of the precise patterns into structures with aspect ratios much larger than those previously achievable.

Abstract: A fully depleted SOI FET and methods of formation are disclosed. The FET includes a layer of semiconductor material disposed over an insulating layer, the insulating layer disposed over a semiconductor substrate. A source, a drain and a body disposed between the source and the drain are formed from the layer of semiconductor material. The layer of semiconductor material is etched such that a thickness of the body is less than a thickness of the source and the drain and such that a recess is formed in the layer of semiconductor material over the body. A gate is formed at least in part in the recess. The gate defines a channel in the body and includes a gate electrode spaced apart from the body by a high-K gate dielectric.

Abstract: A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical planarization processes. In one aspect of the invention, a bi-modal slurry is fabricated by removing a first type of selected abrasive particles from a first abrasive particle solution to form a treated flow of the first solution. The treated flow of the first solution is then combined with a flow of a second solution having a plurality of second abrasive particles. The abrasive particles of the first type are accordingly removed from the first solution separately from the second solution such that the second abrasive particles in the second solution do not affect the removal of the abrasive particles of the first type from the first solution. In another aspect of the invention, a second type of selected abrasive particles are removed from the second solution prior to mixing with the first solution.

Abstract: Nickel film formation is implemented by heating a deposition chamber during deposition of nickel on a substrate or between processing of two or more substrates or both. Embodiments include forming a nickel silicide on a composite having an exposed silicon surface by introducing the substrate to a PVD chamber having at least one heating element for heating the chamber and depositing a layer of nickel directly on the exposed silicon surface of the composite while concurrently heating the chamber with the heating element.

Abstract: A wet etching apparatus and method to shorten processing time and to eliminate formation of unintended mask pattern are described. In the conventional art, after a mask pattern is formed, alien substances such as water mist or stain are left on the substrate. The alien substances act as an etching block in the wet etching process. This generates an unintended mask pattern. The present invention uses ultraviolet light to remove the alien substances prior to the etching process. When the alien substances are removed, the intended mask pattern is generated after the etching process. The wet etching device according to the present invention includes an ultraviolet cleaner and a conveyor to convey substrates to and from the ultraviolet cleaner. Spaces for the ultraviolet cleaner and the conveyor are created in the wet etching apparatus by reducing space for cassettes and reducing space required by the loader.

Abstract: To determine an optimum addition ratio of ethyl alcohol in the etching gas in a plasma etching unit, an ethyl alcohol addition ratio at which the isotropic etching rate of the etching mask is obtained, and on the basis of the obtained ethyl alcohol addition ratio, the optimum addition ratio is determined, by performing an etching process using an etching gas containing ethyl alcohol in the optimum addition ratio, the portions of the bottom antireflective coating which are not covered with the etching mask are removed. Thus, it is possible to provide a novel etching method capable of appropriately removing unnecessary portions of the bottom antireflective coating which are not covered by photoresist without causing much damage to the photoresist used as the etching mask.

Abstract: Variations in the size of a linear pattern resulting from difference in mask pattern layout are prevented by setting the perimeter of the linear pattern per unit area in a specified range irrespective of the type of a semiconductor integrated circuit device or by adjusting a process condition in accordance with type-to-type difference in the perimeter of the linear pattern per unit area.

Abstract: A method for forming an electrical insulating layer on bit lines of the flash memory is disclosed. A conductive layer, a mask layer and a cap layer are sequentially formed on a semiconductor substrate and then are etched to form a plurality of spacing. Afterwards, a dielectric layer is formed on the semiconductor substrate and a planarized layer is then formed on the dielectric layer. The planarized layer and the dielectric layer are etched sequentially wherein the etching rate of the planarized layer is less than that of the dielectric layer. Next, the dielectric layer is etched to remove a portion of the dielectric layer wherein the etching rate of the dielectric layer is higher than that of the cap layer, and thus a spacing dielectric layer is formed on the spacing. Thereafter, the cap layer is stripped wherein the etching rate of the dielectric layer is less than that of the mask layer so that the spacing dielectric layer has a round top and slant sides.

Abstract: A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by chemical mechanical planarization.

Abstract: The present invention provides low cost microfluidic devices having embedded metal conductors. The devices of the invention comprise a electronic component comprising a substrate having a first surface, a layer of electrically-conductive material deposited on a portion of the first substrate surface, a first sublayer of electrically-insulating material deposited on the first substrate surface and on the layer of electrically-conductive material, a second sublayer of electrically-insulating material deposited on the first sublayer of insulating material, and a third sublayer of electrically-insulating material deposited on the layer of dielectric material, and a fluid-handling component having a contoured surface affixed to the electronic component. The devices of the invention are advantageously used for performing electric field lysis and the polymerase chain reaction. The invention further advantageously provides simple, low cost methods for fabricating such microfluidic devices.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.