Abstract: A method of producing suspended elements for electrical connection between two portions of a micro-mechanism that can move relative to one another provides for the formation of a layer of sacrificial material, the formation of the electrical connection elements on the layer of sacrificial material, and the selective removal of the layer of sacrificial material beneath the electrical connecting elements, the layer of sacrificial material being a thin film with at least one adhesive side that can be applied dry to the surface of the micro-mechanism.

Abstract: A large semiconductor crystal is produced by charging a raw material into a crucible in a reactor tube, sealing the reactor tube with a flange on an open end of the tube, pressurizing the interior of the tube to an elevated pressure with an inert gas, heating the tube with an externally arranged heater to melt the raw material to form a raw material melt in the crucible, and solidifying the raw material melt to grow the semiconductor crystal. A second raw material such as a group V element can be introduced as a vapor from a reservoir into the melt in the crucible to form a compound semiconductor material. The flange is sealed to the tube by an elastic seal member, of which the temperature is maintained below 400° C. throughout the process, to protect its elastic sealing properties.

Abstract: A method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform thicknesses may be formed. In particular, a method is provided which includes polishing an upper layer of a topography to expose a first underlying layer and etching away remaining portions of the first underlying layer to expose a second underlying layer. The topography may then be subsequently planarized. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack.

Abstract: An apparatus for solving an edge exclusion problem when polishing a semiconductor wafer includes a rotatable polishing platen with a polishing pad attached to its upper surface. A polishing slurry is deposited on the upper surface of the polishing pad during polishing. Mounted above the polishing pad is a rotatable polishing head for holding a substrate. A non-rotary actuator assembly is coaxially oriented about the outer edge of the polishing head. A ditched ring is removably attached to the bottom surface of the actuator assembly. A multiplicity of conduit grooves are formed in the bottom section of the ditched ring that allows the polishing slurry to travel unimpeded beneath the rotating wafer. A reduced wall thickness at the bottom of the ditched ring is configured to displace wrinkles from the outer edge of the wafer to the outer periphery of the ditched ring. This solves the edge exclusion problem while permitting polishing slurry to pass under the wafer.

Abstract: Ions are implanted into a resist pattern for forming a wiring pattern. Argon is employed as the ion species, for performing ion implantation under 50 keV at 1×1016/cm2. Due to the ion implantation, the thickness of the resist pattern contracts to about 334 nm, i.e., about 75% of the thickness of 445 nm before ion implantation, while the composition of the resist pattern changes for improving resistance against etching for a silicon nitride film and a polysilicon layer. Thus obtained is a method of manufacturing a semiconductor device capable of suppressing critical dimension shift density difference (difference between a critical dimension shift on a rough region having a relatively large space width and that on a dense region having a relatively small space width).

Abstract: A method for use in the fabrication of active plates for pixilated devices, such as active matrix liquid crystal displays, having pixel electrodes (38) and associated address lines (32) formed from a layer of transparent conductive material (53) through which the conductivity of the address lines is improved. The transparent conductive layer (53) and a metal layer (54) are deposited in succession and followed by a shielding layer (60), e.g. of photoresist, which is patterned into a configuration of regions (67,68,69) corresponding to the required pixel dielectrodes and address lines with a property of the layer at these respective regions being different. This enables the regions of this layer corresponding to the pixel electrodes to be selectively etched away, thereby allowing the metal at these regions to be selectively removed while leaving metal at the address lines. The method simplifies the production of low mask mount TFT active plates with improved address line conductivity.

Abstract: A metal-insulator metal (MIM) capacitor structure has a copper layer within a dielectric layer positioned on a substrate, an alloy layer atop the copper layer, a metal oxide layer atop the alloy layer and a top pad layer atop the metal oxide layer.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one-step process or a two-step process. In the one-step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two-step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide.

Abstract: The invention provides a chemical-mechanical polishing slurry comprising a liquid, cerium ions as an oxidizer, an abrasive, and a pH increasing substance. The cerium ions are in the liquid in a quantity equal to the inclusion of at least 0.02 molar ammonium cerium nitrate in the liquid. The abrasive is also included in the liquid. The liquid, the cerium ions and the abrasive jointly have a first pH value. The pH increasing substance increases the first pH value to a second pH value above 1.5.

Abstract: One aspect of the present invention relates to a system and method for monitoring in-situ a chemical composition at or near a surface of a wafer during plasma etch to detect defects The method involves the steps of providing a semiconductor substrate comprising at least one top layer, wherein the semiconductor substrate comprises at least one chemical-containing contaminant; subjecting the semiconductor substrate to a plasma etch process, whereby at least a portion of the top layer is removed; during the plasma etch process, detecting for a presence of the chemical-containing contaminant using one of an Auger Electron Spectroscopy system or Energy Dispersive X-ray Analysis system; and if present, determining whether the presence of the chemical-containing contaminant exceeds a threshold limit.

Abstract: The carbon layer forming method starts a film deposition process of a carbon layer by vapor phase deposition after a content of particles having a particle size of 0.5 &mgr;m or more is adjusted in a film deposition system of the carbon layer to 1000 particles/ft3/min or less. The carbon layer forming method by means of a vapor phase deposition technique such as sputtering or CVD ensures that a high-quality carbon layer having significantly reduced pinholes or cracks can be obtained. Since the carbon protective layer obtained by this method has no cracking and delamination due to pinholes and cracks, the thermal head having the carbon protective layer has a sufficient durability to ensure that high reliability is exhibited over an extended period of time to perform thermal recording of high-quality images consistently over an extended period of operation.

Abstract: A silicon element having macrocavities beneath its exterior surface is fabricated by electrochemical etching of a p-type silicon wafer. Etching at a high current density results in the formation of deep macrocavities overhung by a layer of crystalline silicon. The process works with both aqueous and non-aqueous electrolytes.

Abstract: A semiconductor manufacturing process wherein high aspect ratio deep openings are plasma etched in a dielectric layer using an etchant gas which includes a fluorocarbon, a sulfur-containing gas, an oxygen-containing gas and an optional carrier gas. The etchant gas can include CxFyHz such as C4F8, SO2, O2 and Ar. The combination of the sulfur-containing gas and the oxygen-containing gas provides profile control of the deep openings.

Abstract: There are disclosed a semiconductor wafer which has undulation components on wafer back surface and/or wafer front surface of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm; method for producing a semiconductor wafer by polishing front surface of the semiconductor wafer which is held at its back surface, which utilizes a semiconductor wafer to be polished having undulation components on wafer back surface of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm; and wafer chuck provided with a holding surface for holding a wafer by chucking, wherein the holding surface has undulation components of 10 &mgr;m3 or less represented in terms of power spectrum density at least for the components at a wavelength of 10 mm.

Abstract: Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.

Abstract: The object of the present invention is to provide an aqueous dispersion that can give the required properties for a wide range of uses including electronic materials, magnetic materials, optical materials and polishing materials, and to provide an aqueous dispersion for chemical mechanical polishing (CMP slurry) that gives an adequate polishing rate without creating scratches in polishing surfaces. Another object of the present invention is, to provide a method for manufacture of semiconductor devices using a CMP slurry that can control progressive erosion due to scratches and the like during polishing and that can achieve efficient flattening of working films, and to provide a method for formation of embedded wiring.

Abstract: The photolithography processes for connecting the first conductive film pattern, which is a lower layer such as a gate electrode of a TFT, to a second conductive film pattern, which is an upper layer such as a source/drain electrode of a TFT are reduced by utilizing laminated films and a resist pattern formed thereon having different film thicknesses. Laminated films constituting the source/drain electrode are formed by depositing films on an insulating substrate on which the first conductive film pattern is formed, and the resist pattern is formed on the top layer of the laminated films, and then utilizing the film thickness difference of the resist pattern and the film composition of the laminated films, the short circuited wiring between the gate electrode and the source/drain electrode for an Electro-Static-Discharge protection circuit of the active matrix substrate can be formed by less photolithography processes than that in the manufacturing of the conventional active matrix substrate.

Abstract: The invention encompasses a method of removing at least some of a material from a semiconductor substrate. A feed gas is fed through an ozone generator to generate ozone. The feed gas comprises at least 99.999% O2 (by volume). The ozone, or a fragment of the ozone, is contacted with a material on a semiconductor substrate to remove at least some of the material from the semiconductor substrate. The invention also encompasses another method of removing at least some of a material from a semiconductor substrate. A mixture of ozone and organic solvent vapors is formed in a reaction chamber. At least some of the ozone and solvent vapors are contacted with a material on a semiconductor substrate to remove at least some of the material from the semiconductor substrate.

Abstract: A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.

Abstract: A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.