Abstract: A method of plasma etching of silicon that utilizes the plasma to provide laterally defined recess structures through a mask. The method is based on the variation of the plasma parameters to provide a well-controlled anisotropic etch, while achieving a very high etch rate, and a high selectivity with respect to a mask. A mixed gas is introduced into the vacuum chamber after the chamber is evacuated, and plasma is generated within the chamber. The substrate's surface is exposed to the plasma. Power sources are used for formation of the plasma discharge. An integrated control system is used to modulate the plasma discharge power and substrate polarization voltage levels.

Abstract: Methods and apparatuses for removing material from discrete areas on a semiconductor wafer are described. In one implementation, an etchant applicator is provided having a tip portion. Liquid etchant material is suspended proximate the tip portion and the etchant applicator is moved, together with the suspended liquid, sufficiently close to a discrete area on a wafer to transfer liquid etchant onto the discrete area. In various embodiments the tip portion can comprise fluid permeable materials, fluid-absorbent materials, and/or wick assemblies. An exhaust outlet can be provided operably proximate the tip portion for removing material from over the wafer. The tip portion can be moved to touch the discrete area.

Abstract: A method of patterning a hard mask, the comprising the following steps. A semiconductor structure is provided. A conductor film is formed over the semiconductor structure. An oxide layer is formed over the conductor film. A patterned metal oxide layer is formed over the conductor film. The oxide layer and the conductor film are etched, using the metal oxide layer as a hard mask, to form a patterned structure.

Abstract: Methods and apparatuses for removing material from discrete areas on a semiconductor wafer are described. In one implementation, an etchant applicator is provided having a tip portion. Liquid etchant material is suspended proximate the tip portion and the etchant applicator is moved, together with the suspended liquid, sufficiently close to a discrete area on a wafer to transfer liquid etchant onto the discrete area. In various embodiments the tip portion can comprise fluid permeable materials, fluid-absorbent materials, and/or wick assemblies. An exhaust outlet can be provided operably proximate the tip portion for removing material from over the wafer. The tip portion can be moved to touch the discrete area.

Abstract: A method of producing an infrared sensor on a semiconductor substrate involves defining at least one area on the surface of the semiconductor substrate where a recess is to be created in the semiconductor substrate, depositing a membrane on the surface, applying a radiation absorber to the membrane in the defined area, applying thermoelements with a hot contact in thermal contact with the radiation absorber and a cold contact in thermal contact with the semiconductor substrate. In this method, an opening is provided in the membrane in the defined area, and the semiconductor substrate is etched through the opening.

Abstract: A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element.

Abstract: A method and apparatus for monitoring a process by employing principal component analysis are provided. Correlated attributes are measured for the process to be monitored (the production process). Principal component analysis then is performed on the measured correlated attributes so as to generate at least one production principal component; and the at least one production principal component is compared to a principal component associated with a calibration process (a calibration principal component). The calibration principal component is obtained by measuring correlated attributes of a calibration process, and by performing principal component analysis on the measured correlated attributes so as to generate at least one principal component. A principal component having a feature indicative of at least one of a desired process state, process event and chamber state then is identified and is designated as the calibration principal component.

Abstract: A method of manufacturing a bottom electrode of a capacitor. A substrate has a contact pad formed thereon, a first dielectric layer is formed on the contact pad, and a node contact penetrates through the first dielectric layer and electrically couples to the contact pad. A second dielectric layer is formed on the first dielectric layer and the node contact. A third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the third dielectric layer. A trench is formed to penetrate through the fourth, the third and the second dielectric layer and to expose a surface of the node contact. A conductive layer is formed on the fourth dielectric layer and a sidewall and a bottom of the trench. A fifth dielectric layer is formed on the conductive layer, wherein the fifth dielectric layer fills the trench. A portion of the fifth dielectric layer and a portion of the conductive layer are removed until a surface of the fourth dielectric layer is exposed.

Abstract: A method of passivating an integrated circuit comprising providing an integrated circuit having a top side including a bond pad, depositing a first dielectric over said top side of said integrated circuit, exposing a first area portion of a top side of said bond pad, depositing a second dielectric of one of a material that is substantially impermeable to moisture over said top side of said integrated circuit, and exposing a second area portion of said top side of said bond pad, said second area portion within said first area portion is disclosed.

Abstract: A method for removing chemisorbed halogens from the surface of a silicon wafer after a plasm etching process is described. The removal takes place before the wafer is unloaded from the etching chamber in order to avoid exposure to atmospheric moisture. Exposure to moisture would cause the discharge of the chemisorbed halogen into the ambient causing corrosion of metal surfaces, particulate formation which reduces product yield, and unsafe halogen levels near the etching tool. The method is particularly useful during silicon etching with HBr where considerable amounts of bromine are chemisorbed onto wafer surfaces. After the etching process is complete, and without breaking vacuum, a carrier gas containing water vapor is flowed over the wafer for a brief time period. The chemisorbed bromine reacts with the water vapor and is converted to HBr which is then purged from the chamber.

Abstract: The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation. The processes of the invention are characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a cationic surfactant for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate. The method reduces or eliminates the transfer of topographic variations to levels below the desired planarization level.

Abstract: The invention concerns a method for treating a surface (2) of a semiconductor (1B) and a corresponding treating device. The surface is made by first molecules of the semiconductor having external bonds saturated with hydrogen. The method consists in sending a beam (30)of ions highly charged and with low energy towards the surface, and applying thereto a deceleration voltage U2 in the proximity of the surface. In this way, the ions extract without making contact the electrons of the first molecules, releasing the hydrogen atoms saturating the corresponding external bonds. Then a product saturating the pendant external bonds is sent so as to form second molecules of an insulating compound. The invention is useful for surface cleaning, etching and nano-manufacturing.

Abstract: The present invention provides a semiconductor manufacturing method, a plasma processing method and a plasma processing apparatus for generating a plasma in a processing chamber and carrying out processing on material to be processed by using the plasma, comprising a floating-foreign-particle measuring apparatus including: a light radiating optical system for radiating a light having a desired wavelength and completing intensity modulation at a desired frequency to the processing chamber; a scattered-light detecting optical system for separating a component with the desired wavelength from scattered lights obtained from the processing chamber as a result of radiation of the light by the light radiating optical system, for optically receiving the component and for converting the component into a first signal; and a foreign-particle-signal extracting unit which separates a second signal representing foreign particle floating in the plasma or in an area in proximity to the plasma from a third signal obtained by

Abstract: There is provided a method of forming an interlayer insulating film having a dual-damascene structure, a contact hole and a deep trench mask using an organic silicon film. The shape of polysilane or the like is processed so that polysilane is used as an interlayer insulating film having a dual-damascene structure to control the shape and depth and prevent borderless etching which must be solved when a trench is formed. Polysilane and an insulating film are formed into a laminated structure so as to be integrated with each other after a dry etching step has been completed to easily form a contact hole having a high aspect ratio. The surface of polysilane is selectively formed into an insulating film so as to be used as a mask for use in a dry etching step. Polysilane for use as an anti-reflective film or an etching mask is changed to an oxide film or a nitride film so that films are easily removed.

Abstract: A method for etching substrates, comprising providing at least a first and a second substrate having a coating selected from the group consisting of semiconductor coatings, metallic coatings, and mixtures thereof and introducing at least the first substrate and an etchant into a first tank to etch at least a portion of the coating from the first substrate, introducing at least the second substrate into a second tank and transferring the etchant from the first tank to the second tank to provide etch of at least a portion of the coatings from the second substrate, and removing the etched first substrate from the first tank.

Abstract: A method to form copper interconnects is described. A substrate layer is provided. A first intermetal dielectric layer is deposited overlying the substrate layer. A barrier layer is deposited overlying the first dielectric layer. A thin copper seed layer is deposited overlying the barrier layer. A copper layer is deposited by electrochemical deposition where the copper seed layer initiates the copper layer deposition and where the copper layer is deposited overlying the barrier layer. The copper layer is annealed. The copper layer and the barrier layer are etched through to the underlying first dielectric layer where the copper layer is not protected by a photoresist mask and where the etching through forms conductive traces. A passivation layer composed of a copper-germanium alloy is formed in the exposed surfaces of the copper layer to complete the conductive traces.

Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh

Abstract: A method of fabricating a back surface point contact silicon solar cell having p-doped regions and n-doped regions on the same side by forming a passivating layer on a surface of the cell having opened windows at the p-doped regions and the n-doped regions, b depositing and patterning a first metal layer on the passivating layer in such a way that the first metal layer comes into contact with the p-doped regions and the n-doped regions, by depositing a first insulator layer of polyimide on the first metal layer, by etching and patterning the first insulator layer of polyimide in such a way that the insulator layer has opened windows at, at least one of the p-doped regions and the n-doped regions, by depositing a second insulator layer of polyimide on the first insulator layer of polyimide, by etching and patterning the second insulator layer of polyimide in such a way that the insulator layer has opened windows at, at least one of the p-doped regions and the n-doped regions, by curing the first insulator laye

Abstract: A trench is formed. A first TEOS film is deposited in the trench. Thereafter, the first TEOS film is etched back by a wet etching method up to a planarized surface of a substrate. In this way, seams and a void generated during the first TEOS film deposition step are exposed. This is attained by performing the etching under the conditions that an etching rate for the TEOS film of the upper portion of the trench is larger than that for the TEOS film of the bottom portion of the trench. Thereafter, a second TEOS film is deposited in the trench.

Abstract: A method of performing a nitride strip process step for a plurality of semiconductor wafers includes partially draining the chemical solution within a chemical bath after every nitride strip in which the oxide etch rate is within a specified range. If the oxide etch rate is above the specified range, the partial drain is performed. Once the etch rate falls within the range, the partial drain is performed every time a bath increment signal is received. If the etch rate falls below the specified range, then the bath is completely drained so that the solution may be replaced with fresh chemicals. While it is generally desirable to minimize the amount of field oxide that is removed during the nitride strip process step, the field oxide etch should be maintained at a specified level because, when below that level, the chemical solution silicon content is too high risking the possibility that the silicon will precipitate and cause undesirable effects including coating the wafers being stripped of nitride.