Abstract: A system and method are disclosed for facilitating removal of a defect from a substrate. A charge is applied at the surface of substrate, such as in the form of an ionized gas, to weaken attractive forces between the defect and the substrate. As a result of weakening the attractive forces, a suitable defect removal system may be employed to remove the defect.

Abstract: A method of etching in a plasma etching chamber having an upper electrode and a susceptor is disclosed. The method comprises: setting the upper electrode and the susceptor to a first predetermined distance; performing a first etch at the first predetermined distance for a first predetermined time; setting the upper electrode and the susceptor to a second predetermined distance; and performing a first etch at the second predetermined distance for a second predetermined time.

Abstract: An improved method for making a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A layer of photoresist is deposited and patterned to expose part of the second hard masking layer to define a via. That exposed part of the second hard masking layer is then etched. A second layer of photoresist is deposited and patterned to expose a second part of the second hard masking layer to define a trench. After etching the exposed second part of the second hard masking layer, a via and trench are etched into the dielectric layer, which are then filled with a conductive material.

Abstract: A method of etching a material film formed on a semiconductor wafer loaded onto a reaction chamber of a surface wave coupled plasma etching apparatus having an insulation plate which is capable of generating surface waves by microwaves, and a glass plate placed below the insulation plate, for transmitting the produced surface waves. In the method, the glass plate is rapidly pre-heated by generating an argon (Ar) or xenon (Xe) surface wave coupled plasma which has a high ion density and a large mass, and the material layer is then etched. Therefore, the preheating time of the glass plate can be sharply reduced to less than five minutes. Also, because the etching gas is not used for the heating of the glass, damage to the glass plate can be reduced and generation of polymer on the glass plate is suppressed with an improved etching efficiency, so that failure in etching can also be avoided.

Abstract: Structures for use in conjunction with surface micromachined structures are formed using a two-step etching process. In various exemplary embodiments, the two-step etching process comprises a modified Bosch etch. According to various exemplary embodiments of the two-step etch, first mask and second masks are used to prepare a layer for etching one or more desired structures. The first mask is used to define at least one large feature. The second mask is used to define at least one small feature (small as compared to the at least one large feature). The second mask is formed over the first mask which is formed over the layer. In the first etching step, the at least one small feature is etched into the layer. Then, the second mask is removed using the chemical rinsing agent. In the second etching step, the at least one large feature is etched into the layer such that the at least one small feature propagates further into the layer ahead of the at least one large feature. The first mask is then removed.

Abstract: The present invention discloses a planarization method of memory unit of a flash memory, wherein a patterned polysilicon layer and a silicon nitride layer are formed in turn on a semiconductor substrate. A silicon dioxide layer is then deposited by the HDPCVD technique. Next, a silicon nitride layer is deposited. Finally, the silicon nitride layer and the silicon dioxide layer thereon are simultaneously removed using hot phosphoric acid. Because the CMP technique is not used in the present invention, the problem of micro scratches will not arise. Therefore, the present invention can assure the requirement of high planarity of memory unit of the flash memory, simplify the process flow, increase the tolerance of the etching mask, and effectively enhance the function of memory unit.

Abstract: A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used because no additional resist is required to provide a “margin of error” during the etching to assure the integrity of the barrier layer. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP.

Abstract: A chemical mechanical polishing (CMP) system includes a polishing device including a polishing article. The polishing device holds the semiconductor wafer and provides relative movement between the semiconductor wafer and the polishing article with a slurry therebetween. The CMP system also includes a slurry processor for processing used slurry from the polishing device and for delivering processed slurry to the polishing device. The slurry processor including a metal separator for separating metal particles, polished from the semiconductor wafer, from the used slurry. The slurry can be continuously recirculated during a CMP process without damaging and/or contaminating the layers of the semiconductor wafer.

Abstract: The present invention provides a method of planarization for an inter layer dielectric of an EDRAM. The method comprises defining a periphery circuit region and a memory array area on a semiconductor wafer of the EDRAM, and forming a plurality of MOS transistors and capacitors. As well, both a dielectric layer and a photoresist layer are formed on the semiconductor wafer using the layout patterns of a storage node of thecapacitors as a reverse mask to perform an etching process. Consequently, portions of the photoresist layer in the memory array area are removed while simultaneously etching the dielectric layer in the memory array area by a predetermined depth. Finally, a chemical mechanical polishing process is performed on the dielectric layer to planarize the inter layer dielectric of the EDRAM.

Abstract: A method for planarizing an oxide surface and removing dishing or erosion defect from a semiconductor wafer. An apparatus for carrying out the planarization process on a semiconductor wafer is further described. In the method, a wafer that has metal residues or dishing or erosion defect after a copper CMP process is first rotated at a rotational speed of at least 1000 RPM, while simultaneously a solvent/abrasive particles mixture is injected onto the rotating surface for a sufficient length of time until the metal residues, the dishing or erosion defect is removed. The rotational speed of the semiconductor wafer can be suitably controlled in a range between about 1000 RPM and about 10,000 RPM. For the removal of an oxide layer, a suitable solvent of diluted HF and a suitable abrasive particle such as aluminum oxide may be used.

Abstract: A technique for self-aligned processing of semiconductor device features is disclosed. This technique includes the formation of a semiconductor device with transistor gates having a polysilicon member that extends from the plane of a semiconductor substrate. A coating is deposited on the gates and substrate. Chemical mechanical polishing is performed to remove a portion of the coating to expose a polysilicon surface of the gates without lithographic processing. A recess is formed in the exposed polysilicon surface and at least partially filled with an etch stop material such as silicon nitride. Silicidation of the polysilicon member to form a silicide layer in the recess or a selective chemical vapor deposition on the bottom of the recess with an appropriate metal may be performed before filling the recess with the etch stop material.

Abstract: To provide a method having stable high polishing efficiency in the CMP of an LSI wafer and means for reducing the amount of use of consumable items such as a polishing liquid and a pad, an electric field is applied to the abrasive grains on a pad to attract the abrasive grains into a diffusion layer in the polishing liquid solvent near the surface of the pad, thereby holding the abrasive grains in the diffusion layer.

Abstract: In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and comprising an upper corner at a periphery of the opening, the upper corner having a corner angle with a first degree of sharpness; b) reducing the sharpness of the corner angle to a second degree; c) after reducing the sharpness, forming a layer of material within the opening and over the etch-stop layer; and d) planarizing the material with a method selective for the material relative to the etch-stop layer to remove the material from over the etch-stop layer while leaving the material within the opening.

Abstract: A polishing apparatus is used for polishing a workpiece such as a semiconductor wafer to a flat mirror finish by a combination of chemical polishing and mechanical polishing. The polishing apparatus includes a turntable with a polishing cloth mounted on an upper surface thereof, a top ring for supporting the workpiece to be polished and pressing the workpiece against the polishing cloth, and a dressing tool for dressing the polishing cloth on the turntable. The polishing apparatus further includes a cover which covers an upper surface of the turntable for preventing liquid on the turntable from being scattered, and inserting holes formed in an upper wall of the cover for inserting the top ring and the dressing tool therethrough.

Abstract: Transistors having self-aligned dielectric layers under the source/drain contacts are formed by constructing transistors up to the LDD implant; etching STI oxide selective to Si and nitride to form a self-aligned contact recess; depositing an insulating layer in the bottom of the contact recess; recessing the insulating layer to leave room for a conductive contact layer; depositing the contact layer to make contact on a vertical surface to the Si underneath the gate sidewalls; recessing the contact layer; forming interlayer dielectric and interconnect to complete the circuit.

Abstract: A gallium nitride growth process forms crystalline gallium nitride. The process comprises the steps of providing a source gallium nitride; providing mineralizer; providing solvent; providing a capsule; disposing the source gallium nitride, mineralizer and solvent in the capsule; sealing the capsule; disposing the capsule in a pressure cell; and subjecting the pressure cell to high pressure and high temperature (HPHT) conditions for a length of time sufficient to dissolve the source gallium nitride and precipitate the source gallium nitride into at least one gallium nitride crystal. The invention also provides for gallium nitride crystals formed by the processes of the invention.

Abstract: A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method are disclosed. The method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: A method of manufacturing a semiconductor device using a shallow trench isolation (STI) process comprises the steps of depositing a Si3N4 film (3) by a chemical vapor deposition (CVD) process, polishing a CVD oxide film (6) by a chemical mechanical polishing (CMP). The method further comprises the steps of planarizing with an organic spin-on-glass (SOG) film (7) a rough surface of the silicon substrate resulting from a pattern dependency of polished amounts in the CMP process and etching back evenly the organic SOG film (7) and the CVD oxide film (6) buried in the trench at an etching selectivity ratio of 1.

Abstract: A method of manufacturing a semiconductor substrate includes the steps of laminating a first substrate having a single-crystal semiconductor region with a second substrate having an insulator region, and selectively removing the portion of the first substrate of the laminated substrates where lamination strength is weak.