Abstract: An improved method for etching a pattern in a semiconductor material is based on the formation of an InP grating mask on the semiconductor material. The formation of the InP grating mask involves the formation of a multi-layered structure on the semiconductor material with an etch-stop layer between two InP layers. A photoresist grating mask corresponding to the pattern to be etched in the semiconductor material is then formed on the top InP layer. Subsequently, a non-selective etch is used to penetrate the top InP layer, the etch-stop layer, and the lower InP layer. A suitable stripping solvent is then used to remove the photoresist followed by a selective etch to clear the remaining exposed InP material, remove contaminated material and to expose the underlying semiconductor material in accordance with the pattern to be etched. Additional masking beyond the InP mask is, therefore, not required.

Abstract: A post-etch clean up process for OSG. After the trench (112)/via (114) etch in a dual damascene process, a wet chemistry comprising HF and H2O2 is used to remove residues without etching or damaging the OSG film in the ILD (108) or IMD (110).

Abstract: A method for etching material which does not readily form volatile compounds in a plasma includes providing a plasma etch chamber including a wafer electrode at an initial temperature. The wafer electrode supports a wafer, and the wafer includes a layer of the material which does not readily form volatile compounds in plasma. The wafer is bombarded with charged particles from a plasma generated in the plasma etch chamber to impart thermal energy to the wafer. A reactive gas flow is provided to react with etch products of the material. Bias power is applied to the wafer electrode to impart bombardment energy to the charged particles incident on the wafer from the plasma such that a predetermined temperature is generated on a surface of the wafer wherein the wafer electrode is maintained at about the initial temperature.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: A method detects an etching termination time point at which a to-be-processed layer formed on an underlayer is etched using plasma. Two types of light components of different wavelengths are applied to the to-be-processed layer, during plasma etching, thereby causing light to reflect from the surface of the to-be-processed layer and from a boundary between the to-be-processed layer and the underlayer, those waveforms of two reflected light components of different wavelengths and included in the reflected light, which result from interference, are detected. An approximate etching termination time point is detected on the basis of a phase difference between the detected waveforms.

Abstract: Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.

Abstract: The high density plasma metal etch rate of a conductive material within a dense array of conductive lines is increased to greater than the etch rate of the conductive material in a bordering open field by controlling the source power and the bottom power in a plasma chamber, thereby reducing overetching, resist loss, and oxide loss in the open field, and facilitating planarization.

Abstract: A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by chemical mechanical planarization.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions across the back side of the wafer are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a first surface of a semiconductor wafer includes a polishing pad which polishes the first surface of the semiconductor wafer. The apparatus also includes a first mechanism which is used to hold, or otherwise support, the wafer during polishing, and a second mechanism that is used to apply a non-uniform pressure distribution through the first mechanism, directly onto a second surface of the wafer. The second mechanism is further used to facilitate polishing the first surface of the semiconductor wafer such that the first surface of the semiconductor wafer is evenly polished.

Abstract: A light-emitting and/or light-receiving semiconductor body is produced with one or more semiconductor layers composed of GaAsxP1−x, where 0≦x<1. At least a portion of the surface of the semiconductor layer is first treated with an etching solution H2SO4:H2O2:H2O in a first etching step and then with hydrofluoric acid in a second etching step. The etching results in a surface roughness on the treated portion of the surface of the semiconductor layer.

Abstract: A method of forming a dual damascene structure. A first dielectric layer, an etching stop layer, a second dielectric layer and a hard mask layer are sequentially formed over a substrate. Photolithographic and etching operations are conducted to remove a portion of the hard mask layer, the second dielectric layer, the etching stop layer and the first dielectric layer so that a via opening is formed. A conformal dielectric layer is formed on the surface of the hard mask layer and the interior surface of the via opening. An anisotropic etching operation is carried out to form spacers on the sidewalls of the via opening. A patterned photoresist layer is formed over the hard mask layer. Using the patterned photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench.

Abstract: A composition and a method for planarizing or polishing a surface with the composition are provided. The composition comprises a liquid carrier, a chemical accelerator, and solids comprising about 5-90 wt. % of fumed metal oxide, and about 10-95 wt. % of abrasive particles, wherein about 90% or more of the abrasive particles (by number) have a particle size no greater than 100 nm. The composition of the present invention is useful in planarizing or polishing a surface with high polishing efficiency, uniformity, and removal rate, with minimal defectivity, such as field loss of underlying structures and topography.

Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

Abstract: The invention includes a method of finishing a polycrystal silicon nitride surface. The method of finishing the polycrystal silicon nitride includes providing a polycrystal silicon nitride composite which includes a plurality of silicon nitride crystal grains and a glassy-phase grain boundary medium. The method further includes providing an abrading finishing mixture with the finishing mixture including an abrasive and an oxidant. The method includes concurrently oxidizing the silicon nitride grains and abrading the silicon nitride composite to provide a finished polycrystal silicon nitride surface.

Abstract: A method for etching a surface of an integrated circuit. A layer of photoresist is applied to the surface of the integrated circuit. The layer of photoresist is exposed and developed, and the surface of the integrated circuit is etched with an etchant that contains chlorine. The surface of the integrated circuit is exposed to tetra methyl ammonium hydroxide to neutralize the chlorine, and rinsed with water.

Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.

Abstract: To provide a method having stable high polishing efficiency in the CMP of an LSI wafer and means for reducing the amount of use of consumable items such as a polishing liquid and a pad, an electric field is applied to the abrasive grains on a pad to attract the abrasive grains into a diffusion layer in the polishing liquid solvent near the surface of the pad, thereby holding the abrasive grains in the diffusion layer.

Abstract: A method of making a fuse and a fuse, together with systems and integrated circuits where the fuse provides benefits, are described. A fuse comprising a conductive material is formed on a substrate. A series of dielectric layers having a composite thickness is formed on the substrate and the fuse. The series of dielectric layers serves to insulate a series of conductive layers from each other. The conductive layers are disposed above portions of the substrate. An opening is formed extending through a passivation layer and the series of dielectric layers. The opening exposes a portion of the fuse. Another dielectric layer is formed on the fuse and the fuse may thereafter be programmed by directing a laser beam onto the fuse through the opening.

Abstract: A spherical shaped semiconductor integrated circuit (“ball”) and a system and method for manufacturing same. The ball replaces the function of the flat, conventional chip. The physical dimensions of the ball allow it to adapt to many different manufacturing processes which otherwise could not be used. Furthermore, the assembly and mounting of the ball may facilitates efficient use of the semiconductor as well as circuit board space.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.