Abstract: The present disclosure provides a defining solution for preparing a pixel defining layer configured to define individual pixels on a substrate, comprising: a lyophilic material, a lyophobic material and an initiator, wherein the lyophobic material comprises: a first lyophobic material and a second lyophobic material, and wherein a mass average molecular weight of the first lyophobic material is greater than a mass average molecular weight of the second lyophobic material, and a mass average molecular weight of the lyophilic material is greater than the mass average molecular weight of the first lyophobic material. The present disclosure further provides a display panel, a display apparatus and a method of preparing a pixel defining layer.

Abstract: Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.

Abstract: A display substrate, a method for manufacturing a display substrate, and a display device are provided. The display substrate includes an effective display area, a punch area, and a critical area between the effective display area and the punch area. The critical area of the display substrate includes: a substrate, and at least one first barrier wall on the substrate. The at least one first barrier wall is a convex structure.

Abstract: A method for manufacturing a semiconductor device includes forming a dielectric fin extending along a first direction above a substrate; forming a gate strip extending across the dielectric fin along a second direction different from the first direction; etching the gate strip to break the gate strip into a first gate structure and a second gate structure spaced apart from the first gate structure by the dielectric fin; after etching the gate strip, depositing a high-k dielectric material on the dielectric fin.

Abstract: A display device, includes: a substrate including pixel areas and a transmissive area between the pixel areas; a pixel circuit layer including at least one transistor on each of the pixel areas; and a light-emitting element layer on the pixel circuit layer and including at least one light-emitting element at each of the pixel areas and coupled to the at least one transistor, and a transparent organic layer at the transmissive area, wherein the light-emitting element layer further includes: a first electrode at the pixel areas, a first inorganic layer at the first electrode, an organic layer covering the first inorganic layer and the transparent organic layer, and a second inorganic layer on the organic layer.

Abstract: A display device includes a substrate including a display area and a non-display area disposed around the display area; a fan-out unit disposed in the non-display area and including a first pad unit and a first fan-out line electrically connected to the first pad unit; a first signal line disposed on a different layer from the first fan-out line and including a first area overlapping the first fan-out line; a first switching element disposed on the display area and electrically connected to the first signal line and a first pixel electrode; and a color filter overlapping the first area.

Abstract: A power semiconductor device may include a junction termination region, bounded by a side edge of a semiconductor substrate. The junction termination region may include a substrate layer of a first dopant type, a well layer of a second dopant type, a conductive trench assembly having a first set of conductive trenches, in the junction termination region, and extending from above the substrate layer through the well layer; and a metal layer, electrically connecting the conductive trench assembly to the well layer. The metal layer may include a set of inner metal contacts, electrically connecting a set of inner regions of the well layer to a first set of trenches of the conductive trench assembly; and an outer metal contact, electrically connecting an outer region of the well layer to a second set of conductive trenches of the conductive trench assembly, wherein the outer region borders the side edge.

Abstract: A light-emitting display device includes an organic layer formed to be divided between adjacent subpixels through a change in structure of a bank without the provision of an additional construction, whereby it is possible to prevent lateral leakage of current.

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.

Abstract: A transparent display panel includes a base, a first pixel defining structure and a first light-emitting devices. The first pixel defining structure is disposed on the base and includes a first opening that has a light transmission region and a light-emitting region. The first light-emitting device is disposed on the base and includes an opaque electrode and a light-emitting functional layer. At least part of the opaque electrode is exposed by the first opening, and an orthographic projection of the opaque electrode does not overlap with the light transmission region. The light-emitting functional layer is disposed in the first opening and defined by the first opening. The orthographic projection of the opaque electrode and an orthographic projection of the light-emitting functional layer have an overlapping region, and at least a portion of the overlapping region is within the light-emitting region.

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

Abstract: Provided are a deposition mask, a method of manufacturing a display device using the deposition mask, and a display device. The deposition mask includes a main frame defining a first opening; ribs extending away from a side of the main frame, the ribs being apart from each other and defining second openings; and bridges connecting the ribs to one another across the second openings, wherein the bridges and the ribs form the same top surface, and a thickness of each of the bridges is less than a thickness of each of the ribs.

Abstract: A display device includes a thin film transistor disposed on a base substrate, an insulation layer covering the thin film transistor, an organic light-emitting diode disposed on the insulation layer, a bus electrode and an organic fluoride pattern. The organic light-emitting diode includes a first electrode electrically connected to the thin film transistor, an organic light-emitting layer disposed on the first electrode, and a second electrode disposed on the organic light-emitting layer. The bus electrode is disposed on the second electrode. The organic fluoride pattern is disposed adjacent to the bus electrode.

Abstract: A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the base substrate includes a semiconductor body that can be doped, and a first conductive layer and a second conductive layer that are on the semiconductor body; the first transistor includes a first doped region in contact with the first electrode of the first transistor, and a second doped region in contact with a second electrode of the first transistor, and the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have a same doping type, and are both in the semiconductor body.

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Abstract: The present application provides a method for manufacturing a pixel structure and a display panel. The pixel structure includes a substrate, a plurality of first pixel banks, and a plurality of second pixel banks. The first pixel banks intersect a long side direction of the substrate. The second pixel banks are parallel to the long side direction of the substrate. Light emitting materials with a same color are disposed between two adjacent second pixel banks, so that this pixel design can be compatible with MMG line-bank printing, which alleviates a problem that existing MMG pixel arrangement mode restricts a printing mode.