Patents Examined by Dzung Tran
  • Patent number: 11450719
    Abstract: An organic light-emitting panel, including a substrate, a planarization layer, a reflective layer and a bank layer, is provided. The substrate has a display region and a periphery region beside the display region. The planarization layer is disposed on the substrate and has an indentation. The reflective layer is disposed on the planarization layer. The reflective layer is formed along a sidewall of the indentation. The bank layer is disposed on the planarization layer, covers the indentation, and has a periphery taper surface. The indentation is adjacent to the periphery taper surface and is closer to the display region than the periphery taper surface. A fabrication method of the above organic light-emitting panel is also provided.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 20, 2022
    Assignee: Au Optronics Corporation
    Inventors: Kuo-Jui Chang, Chien-Sen Weng, Ming-Wei Sun
  • Patent number: 11444138
    Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes a base substrate, a pixel definition layer, a light emitting layer and a spacer. The pixel definition layer is configured to define each of subpixels in the display panel and includes a groove structure which is disposed between adjacent subpixels, the spacer is disposed in the groove structure, the light emitting layer is disposed on a side of the pixel definition layer and the spacer away from the base substrate, and a thermal expansion efficient of the spacer is greater than a thermal expansion efficient of the light emitting layer.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: September 13, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Bo Mao, Mengyu Luan, Changjun Jiang, Jun Li, Lang Liu, Zexu Liu, Hongtao Guo
  • Patent number: 11437583
    Abstract: It is an object of the present invention to provide an organic EL device in which, as a highly efficient and highly durable organic EL material, various materials excelling in electron injection/transport performance, hole blocking performance, hole resistance performance, exciton confinement performance, stability in a film state, and durability, are combined so that properties of each material can be effectively demonstrated, thereby achieving (1) high light emission efficiency and power efficiency, (2) low luminescence starting voltage, (3) low practical driving voltage, and (4) particularly long lifetime. An organic EL device including at least a anode, a hole transport layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and a cathode in this order, characterized in that the hole blocking layer includes a compound having a benzoazole structure represented by the following general formula (1).
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 6, 2022
    Assignee: HODOGAYA CHEMICAL CO., LTD.
    Inventors: Kouki Kase, Naoaki Kabasawa, Shunji Mochizuki, Kazuyuki Suruga
  • Patent number: 11430689
    Abstract: A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: August 30, 2022
    Assignee: Infineon Technologies LLC
    Inventors: Rinji Sugino, Fei Wang
  • Patent number: 11430931
    Abstract: The invention describes a circuit assembly comprising a circuit board with a metal core, a pattern of conductive tracks, and a dielectric layer between the metal core and the conductive tracks; at least one circuit component mounted to the circuit board by means of solder interconnects, wherein a solder interconnect is formed between a contact pad of the circuit component and a conductive track; characterized in that the metal core comprises at least one cavity, wherein a cavity is arranged in the vicinity of a solder interconnect. The invention further describes a circuit board for such a circuit assembly, and a method of manufacturing such a circuit assembly.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 30, 2022
    Assignee: Lumileds LLC
    Inventor: Barbara Muelders
  • Patent number: 11417796
    Abstract: A light-emitting apparatus can include a reflective cavity that can reflect visible light within the reflective cavity. The reflective cavity can allow the reflected visible light to exit the reflective cavity only at one or more specified emission locations. A visible light-emitting diode can emit visible light into the reflective cavity. An infrared light-emitting diode can emit infrared light into the reflective cavity. A lens can angularly redirect infrared light and visible light that exit the cavity through the one or more emission locations. The reflective cavity can be formed by surfaces at least partially coated with a coating that is reflective for visible light. The coated surfaces can include a circuit board that supports the light-emitting diodes, an incident surface of the lens, and an extension portion of the lens that extends from a flange to the incident surface of the lens.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 16, 2022
    Assignee: Lumileds LLC
    Inventors: Mehdi Aas, Erno Fancsali, Frans Hubert Konijn, Arjen Gerben Van der Sijde, Nicola Bettina Pfeffer
  • Patent number: 11411207
    Abstract: A display panel and a method of manufacturing the display panel are provided. The display panel includes an array substrate, a pixel definition layer, and spacers. Each of spacers includes a bottom surface and a top surface. A cross-sectional area of the top surface is less than a cross-sectional area of the bottom surface. A horizontal distance from a center to a side of the spacer gradually increases from the top surface to the bottom surface. Moreover, holes of the mask plate corresponding to positions of the spacers are defined, which ensures accuracy of photolithography and display effect of the display panel.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: August 9, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconduetor Display Technology Co., Ltd.
    Inventor: Junjie Wu
  • Patent number: 11404507
    Abstract: A display substrate, a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) array layer on a base substrate; forming a planarization layer covering the TFT array layer; forming a transition layer on the planarization layer, an adhesion between the transition layer and a photoresist is weaker than an adhesion between the planarization layer and the photoresist; forming the photoresist on the transition layer, exposing and developing the photoresist to form a first photoresist pattern; by using the first photoresist pattern as a mask, etching the transition layer to form a first via hole, and etching the planarization layer through the first via hole to form a second via hole, an orthographic projection of the first via hole onto the base substrate overlaps with an orthographic projection of the second via hole onto the base substrate.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: August 2, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guoying Wang, Zhen Song
  • Patent number: 11404332
    Abstract: The present disclosure provides an array substrate, a fabrication method thereof and a display device. The array substrate includes an insulating layer provided with a first via therein. The array substrate further includes a detection structure including a first conductive structure, a second conductive structure and an insulating structure therebetween. The insulating structure is a portion of the insulating layer. The second conductive structure includes a first portion and a second portion which are separated from each other, and the first portion and the second portion partially overlap with the first conductive structure in a thickness direction of the array substrate, respectively. A second via is provided in the insulating structure between overlapping portions of the first portion and the first conductive structure, and a third via is provided in the insulating structure between overlapping portions of the second portion and the first conductive structure.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 2, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Binbin Cao
  • Patent number: 11404442
    Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: August 2, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Wenbin Zhou, Zhiguo Zhao, Zhaoyun Tang, Hai Lin Xiong
  • Patent number: 11404502
    Abstract: A display substrate, a manufacturing method thereof and a display panel are provided. The display substrate includes a base and a pixel defining layer provided on the base, the pixel defining layer includes a plurality of sub-pixel regions, and at least one storage tank defined by the pixel defining layer is provided in each of the plurality of sub-pixel regions, and at an identical height with respect to the base, in a length direction of the storage tank, an end portion of the storage tank and a portion between two end portions of the storage tank differ in wettability to a storage material.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 2, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Minghung Hsu
  • Patent number: 11398536
    Abstract: The present disclosure discloses a display substrate, a production method thereof and a display device. The display substrate includes: a base substrate, a pixel defining layer located on the base substrate, and an organic functional layer located on the pixel defining layer, where the pixel defining layer has opening areas for defining light emitting areas of respective sub-pixels, and contains photo-induced deforming particles; and the organic functional layer covers the opening areas and includes a plurality of parts corresponding to the respective sub-pixels one by one, and the plurality of parts are spaced from each other.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 26, 2022
    Assignees: Hefei BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Kui Gong, Xianxue Duan, Tianzhen Liu, Dongsheng Jiao
  • Patent number: 11397331
    Abstract: Methods and devices to build and use multi-functional scattering structures. The disclosed methods and devices account for multiple target functions and can be implemented using fabrication methods based on two-photon polymerization or multi-layer lithography. Exemplary devices functioning as wave splitters are also described. Results confirming the performance and benefits of the disclosed teachings are also described.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 26, 2022
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Philip Camayd-Munoz, Conner Ballew, Gregory Roberts, Andrei Faraon
  • Patent number: 11394006
    Abstract: A display panel including: a substrate including an opening area and a display area surrounding the opening area; a plurality of display elements, each including a pixel electrode, an emission layer, and an opposite electrode, the plurality of display elements being located in the display area; a thin-film encapsulation layer covering the plurality of display elements and including an organic encapsulation layer and an inorganic encapsulation layer; a plurality of grooves located between the opening area and the display area, the plurality of grooves being concave in a depth direction of the substrate and having an undercut structure; and a partition wall located between neighboring grooves among the plurality of grooves.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 19, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wonwoo Choi, Wooyong Sung, Sooyoun Kim, Junghan Seo, Seoyeon Lee, Hyoungsub Lee, Moonwon Chang, Seunggun Chae
  • Patent number: 11393808
    Abstract: Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Aniket Patil, Hong Bok We, David Fraser Rae
  • Patent number: 11387302
    Abstract: A display device includes: a substrate; a first insulating layer disposed on the substrate and that includes an inorganic insulating material; an oxide semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the oxide semiconductor layer and that includes an inorganic insulating material; and a third insulating layer disposed on a gate electrode disposed on the second insulating layer and that includes an inorganic insulating material. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and a value in the channel region of the oxide semiconductor layer of HC according to equation (1) is less than 30%.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 12, 2022
    Assignee: Samsung Display Co. , Ltd.
    Inventors: Jaebum Han, Younggil Park, Junghwa Park, Nari Ahn, Sooim Jeong
  • Patent number: 11387299
    Abstract: An embodiment provides a display device including an insulating layer which is continuous between opposed ends of two adjacent lower electrodes from an upper part of one of the ends to an upper part of the other end, a first organic layer which is disposed over the lower electrodes and the insulating layer, a second organic layer which is disposed over the lower electrodes and the insulating layer with the first organic layer interposed therebetween and includes a light emitting layer, and a second electrode which covers the organic layer. The upper face of the insulating layer includes a recess between the two lower electrodes. The aspect ratio of the recess is 0.5 or more.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: July 12, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobutaka Ukigaya
  • Patent number: 11387308
    Abstract: The present application discloses an array substrate having a plurality of first thin film transistors and a plurality of second thin film transistors. Each of the plurality of first thin film transistors includes a silicon active layer. The array substrate includes a base substrate; a silicon layer having a plurality of silicon active layers respectively for the plurality of first thin film transistors; and a UV absorption layer on a side of the silicon layer distal to the base substrate, and including a plurality of UV absorption blocks. Each of the plurality of UV absorption blocks is on a side of the one of the plurality of silicon active layers distal to the base substrate, and is insulated from the one of the plurality of silicon active layers.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 12, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Feng Zhang, Zhijun Lv, Wenqu Liu, Liwen Dong, Shizheng Zhang, Ning Dang, Zhiyong Liu
  • Patent number: 11387297
    Abstract: An OLED display substrate, a manufacturing method thereof and a display device are provided. The OLED display substrate includes a TFT array layer, a first electrode, a pixel definition layer, an OEL layer and a second electrode arranged on a base substrate. The pixel definition layer is configured to define a plurality of subpixel regions. A reflection structure surrounds each subpixel region and is capable of reflecting light beams from the OEL layer and beyond an escaping cone in such a manner as to enable at least parts of the light beams to enter the escaping cone.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 12, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lujiang Huangfu, Xing Fan, Dan Wang, Xiaowei Xu, Liangjian Li
  • Patent number: 11380785
    Abstract: A semiconductor device includes a substrate, a gate structure, semimetallic source/drain structures, and source/drain contacts. The gate structure is over the substrate. The semimetallic source/drain structures are respectively on opposite sides of the gate structure, in which a band structure of each of the semimetallic source/drain structures has a valence band and a conduction band at different symmetry k-points. The source/drain contacts land on top surfaces of the semimetallic source/drain structures, respectively.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Sheng-Kai Su