Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

Abstract: A display device may include a substrate, pixels, and a crack mitigation structure. The substrate may include a main region, a sub-region, and a bending region. The bending region may be connected between the main region and the sub-region and may include a curved outline section. The pixels may be disposed on the main region. The crack mitigation structure may be disposed on the bending region. A section of the crack mitigation structure may be substantially parallel to the curved outline section.

Abstract: A method for manufacturing an array substrate includes: providing a base substrate; forming gate lines and data lines intercrossing each other, the gate lines and the data lines define multiple pixel units. Multiple pixel regions are formed in each pixel unit, a display electrode having a slit is formed in each pixel region. Each data line includes multiple data line segments. In each pixel unit, each of a part of the pixel regions has a display electrode whose slit is parallel to a data line segment adjacent to this pixel region; each of another part of the pixel regions has a display electrode whose slit is non-parallel to a data line segment adjacent to this pixel region. The display electrodes in each of the pixel units are located at a same side of the gate line to which the pixel unit where the display electrodes are located is coupled.

Abstract: Disclosed are a display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a base substrate, and a multilayered functional film layer on the base substrate. The multilayered functional film layer is provided with an opening penetrating through the multilayered functional film layer. A light-shielding film is on a side wall of the opening.

Abstract: A semiconductor device in which a first chip and a second chip are stacked including a first wiring line and a second wiring line by which the first chip and the second chip are electrically connected. The first wiring line and the second wiring line each include a bonding portion for bonding one of a plurality of conductive patterns placed in the first chip and one of a plurality of conductive patterns placed in the second chip. The number of bonding portions included in the first wiring line is larger than the number of bonding portions included in the second wiring line.

Abstract: Disclosed is a display device. The display device includes a substrate having an active area and a non-active area, a thin film transistor arranged on the active area of the substrate, at least two planarization layers arranged on the thin film transistor, signal links arranged on the non-active area of the substrate, and an outer cover layer spaced apart from the at least two planarization layers and configured to overlap upper and side surfaces of the signal links, thus preventing or reducing damage to the signal links.

Abstract: Provided are a display substrate, a manufacturing method thereof and a display device. The display substrate includes a base and a plurality of subpixels arranged on the base in an array form. Each subpixel includes a light-emitting element, a subpixel driving circuitry coupled to the light-emitting element, and a light-emission detection circuitry configured to detect luminescence of light emitted by the light-emitting element. The light-emission detection circuitry includes a first control transistor and a PIN-type photodiode laminated in that order in a direction away from the base, a first electrode of the first control transistor is coupled to a cathode of the PIN-type photodiode, and an orthogonal projection of the first control transistor onto the base at least partially overlaps an orthogonal projection of the PIN-type photodiode onto the base. The display substrate provided by the present disclosure is used for display.

Abstract: Embodiments of the present disclosure relate to a display device including a substrate, an optical device located under the substrate in a display area, and a subpixel layer located over the substrate in the display area, wherein the subpixel layer includes at least one of first transistor with a first characteristic are located at a first area overlapping with the optical device, and at least one of second transistor with a second characteristic are located at a second area not overlapping with the optical device.

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

Abstract: The present disclosure relates to the field of display technology, and proposes a display panel, a preparation method thereof, and a display apparatus. The display panel includes an array substrate, a planarization layer group, and a plurality of sub-pixels. The array substrate includes a switch array formed by a plurality of switch units. The planarization layer group is provided on the array substrate, and nano-scale grooves are provided on the planarization layer group. The sub-pixels are provided on a side of the planarization layer group away from the array substrate. The sub-pixel includes a plurality of first electrodes, wherein the first electrode is connected to the switch unit of the array substrate, a nano-scale second gap is provided between two adjacent first electrodes, and an orthographic projection of the second gap on the array substrate is located within an orthographic projection of the groove on the array substrate.

Abstract: The present disclosure provides a substrate comprising a printing area, wherein the printing area comprises a flat surface and a plurality of separation structures projecting from the flat surface, wherein the plurality of separation structures divide the printing area into a plurality of micro-areas, and in each of the micro-areas, a circular region containing no separation structure has a maximum diameter between 5 ?m and 10 ?m. The present disclosure further provides a light emitting device comprising the substrate and a method for manufacturing the substrate.

Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.

Abstract: A display device includes a substrate, a first semiconductor pattern on the substrate and including a semiconductor layer of a first transistor, a first gate insulator on the substrate, a first conductive layer on the first gate insulator and including a first gate electrode of the first transistor and a first electrode of the capacitor connected to the first gate electrode of the first transistor, a first interlayer dielectric on the first gate insulator, a second semiconductor pattern on the first interlayer dielectric and including a semiconductor layer of a second transistor and a second electrode of the capacitor, a second gate insulator on the first interlayer dielectric, a second conductive layer on the second gate insulator and including a gate electrode of the second transistor and a third semiconductor pattern between the second semiconductor pattern and any one of the first conductive layer and the second conductive layer.

Abstract: A display device and a method of manufacturing a display device are provided. A display device includes a lower conductive pattern disposed on a substrate, a lower insulating layer disposed on the lower conductive pattern, the lower insulating layer including a first lower insulating pattern including an overlapping region overlapping the lower conductive pattern, and a protruding region. The display device includes a semiconductor pattern disposed on the first lower insulating pattern and having a side surface, the side surface being aligned with a side surface of the first lower insulating pattern or disposed inward from the side surface of the first lower insulating pattern, a gate insulating layer disposed on the semiconductor pattern, a gate electrode disposed on the gate insulating layer, and an empty space disposed between the substrate and the protruding region of the first lower insulating pattern.

Abstract: A light-emitting device includes: a first electrode; a second electrode facing the first electrode; light-emitting units in the number of n between the first electrode and the second electrode; and a charge-generation unit(s) in the number of n?1 between the adjacent light-emitting units. The light-emitting units each include an emission layer, and at least one of the charge-generation unit(s) includes an n-type charge-generation layer, a p-type charge-generation layer, and an interlayer between the n-type charge-generation layer and the p-type charge-generation layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.

Abstract: The present disclosure provides a defining solution for preparing a pixel defining layer configured to define individual pixels on a substrate, comprising: a lyophilic material, a lyophobic material and an initiator, wherein the lyophobic material comprises: a first lyophobic material and a second lyophobic material, and wherein a mass average molecular weight of the first lyophobic material is greater than a mass average molecular weight of the second lyophobic material, and a mass average molecular weight of the lyophilic material is greater than the mass average molecular weight of the first lyophobic material. The present disclosure further provides a display panel, a display apparatus and a method of preparing a pixel defining layer.

Abstract: Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate comprising a memory region and a logic region; forming a memory gate in or on the memory region; forming a plurality of first poly-silicon gates on the memory region and surrounding the memory gate; and forming a plurality of second poly-silicon gates on the logic region simultaneously with the formation of the first poly-silicon gates.

Abstract: A display device, includes: a substrate including pixel areas and a transmissive area between the pixel areas; a pixel circuit layer including at least one transistor on each of the pixel areas; and a light-emitting element layer on the pixel circuit layer and including at least one light-emitting element at each of the pixel areas and coupled to the at least one transistor, and a transparent organic layer at the transmissive area, wherein the light-emitting element layer further includes: a first electrode at the pixel areas, a first inorganic layer at the first electrode, an organic layer covering the first inorganic layer and the transparent organic layer, and a second inorganic layer on the organic layer.