Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.

Abstract: A display apparatus includes: a semiconductor layer on a substrate; a gate insulating layer on the substrate and covering the semiconductor layer; a gate electrode on the gate insulating layer and at least partially overlapping the semiconductor layer; an interlayer insulating layer on the gate electrode; and an electrode layer on the interlayer insulating layer and electrically connected to the semiconductor layer, wherein the interlayer insulating layer comprises a first portion and a second portion extending from the first portion, and the electrode layer is on the first portion of the interlayer insulating layer, and a step is provided by a difference in thicknesses of the first portion and the second portion.

Abstract: A display device includes a base substrate, a pixel defining layer disposed on the base substrate and including a first opening, a light emitting structure disposed in the first opening of the pixel defining layer, a thin film encapsulation layer disposed on the light emitting structure, a touch electrode disposed on the thin film encapsulation layer, an insulating pattern disposed on the touch electrode and including a second opening which overlaps the first opening, and a high refractive layer disposed on the insulating pattern, the high refractive layer including a plurality of grid patterns disposed on a top surface of the high refractive layer, and a refractive index higher than a refractive index of the insulating pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flow able oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

Abstract: An optoelectronic device includes a semiconductor substrate, wherein a first transport layer is formed on a first partial region of the semiconductor substrate; a first insulation layer is formed on a second partial region around the first partial region; the first transport layer is formed on the first insulation layer; an interface layer is formed on the first transport layer; a light-emitting material layer containing perovskite material is formed on the interface layer; a second insulation layer is formed on the light-emitting material layer in the second partial region and on the light-emitting material layer near a second partial region side in the first partial region, so that the characteristic size of a single light-emitting pixel or effective working region is adjustable.

Abstract: A display device includes a plurality of pixels, first to nth scanning lines, and a first semiconductor film. The plurality of pixels is arranged in first to nth rows and first to mth columns. The first to nth scanning lines are electrically connected to the pixels in the respective first to nth rows. The first semiconductor film overlaps with at least one of first to kth scanning lines. A display region has a cutoff intersecting the first to nth rows, and the first semiconductor film is located in the cutoff. Each of the plurality of pixels includes a light-emitting element (OLED) and a transistor electrically connected to the OLED and having a second semiconductor film. The first semiconductor film and the second semiconductor film exist in the same layer. n and m are each a natural number larger than 1, and k is a natural number smaller than n.

Abstract: An image sensor includes a substrate having a plurality of pixel regions, a lower layer on the substrate; a plurality of color filters on the lower layer, and a micro-lens layer on or covering top surfaces of the color filters. The micro-lens layer extends to a location between two of the color filters and contacts the lower layer on one of the pixel regions. The color filters are spaced apart from the lower layer.

Abstract: A display panel includes a first defining layer, a first recessed layer, a flat layer, and a pixel unit layer that are laminated on a base substrate in sequence. The pixel unit layer includes a plurality of sub-pixels. The first defining layer defines one or more defining regions on the base substrate, and the one or more defining regions corresponding to part or all of the plurality of sub-pixels. A surface of the first recessed layer in each defining region is recessed.

Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.

Abstract: The embodiments relate to a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a wafer, in the wafer there being provided with a scribe line, in the scribe line there being provided with a test pad, a first test structure, and a second test structure; the second test structure being positioned below the first test structure, and a transverse pitch between the second test structure and the first test structure being at least equal to a width of the test pad; forming a protective layer on the wafer, the protective layer at least covering the scribe line; and performing exposure and development on the protective layer, such that a thickness of the protective layer remained above the first test structure is greater than that of the protective layer remained above the second test structure.

Abstract: The present disclosure relates to a flexible display device including: a substrate over which a thin film transistor is disposed, an intermediate layer disposed to cover the thin film transistor, a first electrode located on the intermediate layer and connected to the thin film transistor, a bank located on the intermediate layer and the first electrode and defining a first region exposing a part of the intermediate layer, a second region exposing a part of the first electrode, and a third region excluding the first and second regions, a first structure located in the first region defined by the bank and tapered toward the substrate, an organic light emitting layer located on the first electrode exposed in the second region, and a second electrode disposed on the organic light emitting layer. Both lateral surfaces of an inverse-tapered structure are disposed to contact the bank, and as a result, corresponding adhesion can be improved, and peeling defects can be reduced or corrected.

Abstract: A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.

Abstract: A display panel includes: a substrate, a pixel-defining layer disposed on the substrate, and a conductive pattern, a light-emitting layer and a cathode layer which are laminated in a direction perpendicular to and away from the substrate. The pixel-defining layer is configured to define a plurality of pixel regions and a non-pixel region outside the pixel regions on the substrate. The conductive pattern includes: an auxiliary electrode layer disposed in the non-pixel region, wherein a groove is formed in a side wall of the auxiliary electrode layer. The cathode layer includes: a first portion disposed in the pixel region and a second portion disposed in the non-pixel region. The second portion of the cathode layer extends into the groove and is in contact with the groove.

Abstract: Disclosed is a display device. The display device includes a substrate having an active area and a non-active area, a thin film transistor arranged on the active area of the substrate, at least two planarization layers arranged on the thin film transistor, signal links arranged on the non-active area of the substrate, and an outer cover layer spaced apart from the at least two planarization layers and configured to overlap upper and side surfaces of the signal links, thus preventing or reducing damage to the signal links.

Abstract: An organic light emitting display device is disclosed. The organic light emitting display device includes a first light emitting part between an anode and a cathode, the first light emitting part having a first light emitting layer, and a second light emitting part between the first light emitting part and the cathode, the second light emitting part having a second light emitting layer and a third light emitting layer, wherein the second light emitting layer includes a hole-type host and a first electron-type host, and the third light emitting layer includes a first electron-type host and a second electron-type host.

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

Abstract: Provided are a display panel and a method of fabricating the same. The display panel includes a display region including a first pixel region where a plurality of pixels are disposed, a sensing region including a second pixel region where a plurality of pixel groups are disposed, and a light transmitting part disposed between the pixel groups. At least the second pixel region includes a light shield layer, and the light shield layer includes an opening hole corresponding to the light transmitting part.

Abstract: A display device includes a supporting substrate including a polymeric material, base substrate disposed on an upper surface of the supporting substrate, a pixel array disposed in a display area of the base substrate, a transfer wiring disposed in a bending area of the base substrate and electrically connected to the pixel array, and an organic filling portion disposed under the transfer wiring in the bending area. The base substrate includes an organic film including a polymeric material, and an inorganic barrier film overlapping the organic film and extending outwardly from an edge of the organic film. The organic filling portion contacts the organic film of the base substrate.