Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

Abstract: Disclosed is an organic light emitting diode display device. The disclosed organic light emitting diode display device includes an overcoat layer disposed on a substrate that is divided into an emissive area and a non-emissive area, and has multiple micro lenses in the emissive area and at least one depression in the non-emissive area. The organic light emitting diode display device further includes: a first electrode disposed on the overcoat layer, wherein the first electrode is disposed in the entire emissive area and in a part of the non-emissive area; a bank pattern disposed in the non-emissive area so as to be superposed on the depression; an organic light emitting layer disposed on the substrate; and a second electrode disposed on the organic light emitting layer. Accordingly, the organic light emitting diode display device may prevent light leakage.

Abstract: A semiconductor storage device includes a third semiconductor layer and a fourth semiconductor layer. The third semiconductor layer has a first width; the third semiconductor layer and a first insulating layer are disposed apart with a first distance; the third semiconductor layer and a second insulating layer are disposed apart with a second distance; the fourth semiconductor layer has a second width; the fourth semiconductor layer and the first insulating layer are disposed apart with a third distance; and the fourth semiconductor layer and the second insulating layer are disposed apart with a fourth distance. A shorter one of the first distance and the second distance is shorter than a shorter one of the third distance and the fourth distance, and the first width is larger than the second width.

Abstract: A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.

Abstract: Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.

Abstract: Provided is a solar cell and a photovoltaic module. The solar cell includes a silicon substrate, and the silicon substrate includes a front surface and a back surface arranged opposite to each other. P-type conductive regions and N-type conductive regions are alternately arranged on the back surface of the silicon substrate. Front surface field regions are located on the front surface of the silicon substrate and spaced from each other. The front surface field regions each corresponds to one of the P-type conductive regions or one of the N-type conductive regions. At least one front passivation layer is located on the front surface of the silicon substrate. At least one back passivation layer is located on surfaces of the P-type conductive regions and N-type conductive regions.

Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

Abstract: Methods of fabricating solar cell emitter regions using substrate-level ion implantation, and resulting solar cells, are described. In an example, a method of fabricating a solar cell involves forming a lightly doped region in a semiconductor substrate by ion implantation, the lightly doped region of a first conductivity type of a first concentration. The method also involves forming a first plurality of dopant regions of the first conductivity type of a second, higher, concentration by ion implantation, the first plurality of dopant regions overlapping with a first portion of the lightly doped region. The method also involves forming a second plurality of dopant regions by ion implantation, the second plurality of dopant regions having a second conductivity type of a concentration higher than the first concentration, and the second plurality of dopant regions overlapping with a second portion of the lightly doped region and alternating with but not overlapping the first plurality of dopant regions.

Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

Abstract: A display panel includes a substrate; a first metal layer comprising a gate of a driving transistor; a second metal layer comprising a capacitor plate of a storage capacitor; a third metal layer, located on one side of the second metal layer away from the substrate and comprising a data line. An orthographic projection of the data line on the substrate is non-overlapped with the orthographic projection of the gate projected on the substrate; and a first shielding electrode, having a fixed potential. A part of the orthographic projection of the gate projected on the substrate is located in an orthographic projection of the first shielding electrode projected on the substrate, and the rest part of the orthographic projection of the gate projected on the substrate is located in the orthographic projection of the capacitor plate projected on the substrate.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor structure, a second semiconductor structure opposite to the first semiconductor structure, and an interface layer between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second semiconductor structure includes a plurality of peripheral circuits electrically connected to the memory stack. The interface layer includes single crystalline silicon and a plurality of interconnects between the memory stack and the peripheral circuits.

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.

Abstract: A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.

Abstract: Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure.

Abstract: The present disclosure provides a photodiode, a manufacturing method thereof, and a display screen. The photodiode includes: a first electrode including a first sub-part and a second sub-part disposed at an interval, wherein the second sub-part includes a first end and a second end; a connecting part disposed on the first sub-part, the first end, and a substrate corresponding to a gap between the first sub-part and the second sub-part; and a light converting part and a second electrode disposed on the second end in sequence.

Abstract: In a light detection device 1 the plurality of pad electrodes are arranged on the semiconductor substrate. Each of the plurality of wires is connected to the pad electrode corresponding thereto. A stitch bond of a corresponding wire is formed on each pad electrode. A distance between each pad electrode and a cell corresponding to the pad electrode is smaller than a distance between the pad electrodes connected to mutually different cells of the cells. The plurality of pad electrodes are arranged in a first region and a second region that are spaced apart from each other with a light receiving region interposed therebetween. The pad electrode corresponding to a cell is arranged in the first region. The pad electrode corresponding to a cell is arranged in the second region.