Patents Examined by Earl N. Taylor
  • Patent number: 10930812
    Abstract: A fully automated fabrication method and system utilizing a single additive manufacturing platform to fabricate solar cell panels without human-touch labor. The system includes a computer and a robotic arm having a machine vision device and a tool changer to which tools are releasably secured. In an exemplary embodiment, the fabrication method uses pre-fabricated substrates wherein the computer controls the robotic arm to deposit an adhesive layer on a pre-fabricated substrate and thereafter place solar cells on the adhesive layer. The solar cells become bonded to the substrate when the adhesive layer cures. The computer then controls the robotic arm to print electrical connections and electrical bus bars on the substrate with electrically conductive ink in order to electrically connect the solar cells. After the electrically conductive ink cures, the computer controls the robotic arm to spray an encapsulating material over the solar cells and substrate.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: February 23, 2021
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: John A Carr, Furman VanDrake Thompson, II, Austin T Bumbalough
  • Patent number: 10923518
    Abstract: An image sensor and a method of fabricating the same are provided. The image sensor includes a substrate including photoelectric elements, a first color filter disposed on the substrate, a second color filter disposed on the substrate to be adjacent to the first color filter, a covering film disposed between sidewalls of the first and second color filters, and an air gap formed in the covering film.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong Ki Kim, Jung Chak Ahn, In Sung Joe
  • Patent number: 10923345
    Abstract: Systems and methods are described herein for growing epitaxial metal oxide as buffer for epitaxial III-V layers. A layer structure includes a base layer and a first rare earth oxide layer epitaxially grown over the base layer. The first rare earth oxide layer includes a first rare earth element and oxygen, and has a bixbyite crystal structure. The layer structure also includes a metal oxide layer epitaxially grown directly over the first rare earth oxide layer. The metal oxide layer includes a first cation element selected from Group III and oxygen, and has a bixbyite crystal structure.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: February 16, 2021
    Assignee: IQE plc
    Inventors: Rytis Dargis, Andrew Clark, Rodney Pelzel
  • Patent number: 10916484
    Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Robert Fehler, Francesca Arcioni, Christian Geissler, Walter Hartner, Gerhard Haubner, Thorsten Meyer, Martin Richard Niessner, Maciej Wojnowski
  • Patent number: 10903450
    Abstract: A display device according to the present invention includes a display region arranged with a plurality of pixels, and a sealing layer covering the display region, wherein the sealing layer includes an insulation layer having a density pattern, the density pattern is a pattern including a low density region and a high density region, the low density region has the insulation layer with a lower density than an average density within the display region of the insulation layer, and the high density region has the insulation layer with a higher density than an average density within the display region of the insulation layer.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 26, 2021
    Assignee: Japan Display Inc.
    Inventor: Hiraaki Kokame
  • Patent number: 10903151
    Abstract: A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10896991
    Abstract: Disclosed are methods for the surface cleaning and passivation of PV absorbers, such as CdTe substrates usable in solar cells, and devices made by such methods. In some embodiments, the method involves an anode layer ion source (ALIS) plasma discharge process to clean and oxidize a CdTe surface to produce a thin oxide layer between the CdTe layer and subsequent back contact layer(s).
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 19, 2021
    Assignee: First Solar, Inc.
    Inventors: Changming Jin, Sanghyun Lee, Jun-Ying Zhang
  • Patent number: 10892192
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
  • Patent number: 10886379
    Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has, on a SOI substrate thereof having a semiconductor substrate, an insulating layer, and a semiconductor layer, a gate insulating film having an insulating film and a high dielectric constant film. The high dielectric constant film has a higher dielectric constant than a silicon oxide film and includes a first metal and a second metal. In the high dielectric constant film, the ratio of the number of atoms of the first metal to the total number of atoms of the first metal and the second metal is equal to or more than 75%, and less than 100%.
    Type: Grant
    Filed: August 4, 2018
    Date of Patent: January 5, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Tetsuya Yoshida
  • Patent number: 10886439
    Abstract: Embodiments of the invention include a semiconductor light emitting device including a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. A wavelength converting structure is disposed in a path of light emitted by the light emitting layer. A diffuse reflector is disposed along a sidewall of the semiconductor light emitting device and the wavelength converting structure. The diffuse reflector includes a pigment. A reflective layer is disposed between the diffuse reflector and the semiconductor structure. The reflective layer is a different material from the diffuse reflector.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 5, 2021
    Assignee: Lumileds LLC
    Inventors: Dawei Lu, Oleg Shchekin
  • Patent number: 10879172
    Abstract: Semiconductor structures are provided. A semiconductor structure includes a substrate, a conductive plate of a first metal layer over the substrate, a first resistor material of a resistor layer over the conductive plate, a high-K material formed between the first resistor material and the conductive plate, a first conductive line of a second metal layer over the resistor layer, and a first via formed between the first conductive line and the first resistor material. The conductive plate, the first resistor material and the high-K material form a capacitor between the first and second metal layers. The first distance between the first resistor material and the conductive plate is less than the second distance between the first resistor material and the first conductive line.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiefeng Jeff Lin, Hsiao-Lan Yang, Chih-Yung Lin, Chung-Hui Chen, Hao-Chieh Chan
  • Patent number: 10867940
    Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Patent number: 10861870
    Abstract: A semiconductor stacked device include a first plurality of device layers separated from one another by a first plurality of dielectric layers, a first electrically conductive via coupled to a contact portion of a device layer of the first plurality of the device layers, a second plurality of device layers separated from one another by a second plurality of dielectric layers, and a second electronically conductive via coupled to a contact portion of a device layer of the second plurality of the device layers. The first electronically conductive via extends to a frontside of the semiconductor stacked device and the second electrically conductive via extends to a backside of the semiconductor stacked device. The first plurality of device layers form a stair pattern in a first direction and the second plurality of device layers form a stair pattern in a second direction inverted from the first direction.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Morrow, Rishabh Mehandru
  • Patent number: 10854614
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. A support layer and a mold layer are partially etched off from the substrate, to form a mold pattern and a support pattern on the substrate such that a contact hole is formed through the support pattern and the mold pattern and an interconnector is exposed therethrough. A lower electrode layer is formed on the mask pattern to fill the contact hole, and a lower electrode is formed in the contact hole by partially removing the lower electrode layer and the mask pattern. The lower electrode is contact with the interconnector and is supported by the support pattern having the same thickness as the support layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pyung-Ho Kim, Seong-Mo Koo, Kuk-Han Yoon, Ki-Youl Kim, Yong-Hwan Kim
  • Patent number: 10847563
    Abstract: A wearable system includes a stacked photodetector assembly including a first wafer including a single photon avalanche diode (SPAD), the first wafer having a thickness T1 configured to minimize absorption by the first wafer of photons included in light incident upon the first wafer while the SPAD is in a disarmed state, and a second wafer having a thickness T2 including a fast gating circuit electrically coupled to the SPAD and configured to arm and disarm the SPAD, the second wafer bonded to the first wafer in a stacked configuration. The fast gating circuit includes a capacitor configured to be charged, while the SPAD is in the disarmed state, with a bias voltage by a voltage source, and supply, while the SPAD is in an armed state, the bias voltage to the SPAD such that a voltage across the SPAD is greater than a breakdown voltage of the SPAD.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: November 24, 2020
    Assignee: HI LLC
    Inventors: Ryan Field, Husam Katnani, Bruno Do Valle, Rong Jin, Jacob Dahle
  • Patent number: 10840352
    Abstract: Nanowire transistors including embedded dielectric spacers to separate a gate electrode from source and drain regions of the transistor. Embedded spacers are disposed within interior sidewalls of a passage through which the gate electrode wraps around a semiconductor filament. The presence of these embedded spacers may dramatically reduce fringe capacitance, particularly as the number of wires/ribbons/filaments in the transistor increases and the number of interior gate electrode passages increases. In some advantageous embodiments, embedded dielectric spacers are fabricated by encapsulating external surfaces prior to those surfaces becoming embedded within the transistor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Seung Hoon Sung, Jack T. Kavalieros, Sanaz K. Gardner
  • Patent number: 10840349
    Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu, Choonghyun Lee, Heng Wu
  • Patent number: 10823697
    Abstract: The present disclosure provides a thin film transistor, a sensor, a biological detection device and a method. The thin film transistor includes a substrate, a first gate, a first dielectric layer, a source, a drain, a semiconductor layer, a second dielectric layer, and a second gate. The first gate is on the substrate. The first dielectric layer is on the substrate and the first gate. The source, the drain, and the semiconductor layer are on a side of the first dielectric layer facing away from the first gate. The second dielectric layer is on the first dielectric layer and the semiconductor layer. A material of the second dielectric layer is a solid state electrolyte material. The second gate is on a side of the second dielectric layer facing away from the semiconductor layer.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 3, 2020
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Xiaochen Ma
  • Patent number: 10797091
    Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Patent number: 10797017
    Abstract: An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Po-Chen Lin, Ra-Min Tain, Chun-Hsien Chien, Chien-Chou Chen