Patents Examined by Earl N. Taylor
  • Patent number: 11502214
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors used with a broadband signal and methods of manufacture. The structure includes: a first photodetector; a second photodetector adjacent to the first photodetector; a first airgap of a first size under the first photodetector structured to detect a first wavelength of light; and a second airgap of a second size under the second photodetector structured to detect a second wavelength of light.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: November 15, 2022
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Siva P. Adusumilli, Mark D. Levy, Yusheng Bian
  • Patent number: 11495688
    Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: November 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu, Zhenxing Bi
  • Patent number: 11488938
    Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, George E. Pax
  • Patent number: 11482630
    Abstract: The invention relates to a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell. The object of the invention is to propose a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell, in which the effects on materials caused by irradiation of the sun-facing side are further minimized. In addition, the method should also be applicable to silicon solar cells in which the emitter layer has a high sheet resistance.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: October 25, 2022
    Assignee: CE CELL ENGINEERING GMBH
    Inventor: Hongming Zhao
  • Patent number: 11462440
    Abstract: A packaging structure is provided. The packaging structure includes a plurality of first chips; and a molding layer between adjacent first chips. The molding layer covers a sidewall of the first chip and exposes a top surface of the first chip.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: October 4, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jian Gang Lu, Fu Cheng Chen
  • Patent number: 11456403
    Abstract: A method is provided for producing a microelectronic device having a subsequent grating of reliefs of which at least one wall is slanted, the method including providing a structure including a base, and an initial grating of reliefs, each relief having at least one proximal end in contact with the base, a distal end, and at least one wall extending between the proximal end and the distal end; and laying the reliefs of the initial grating on one another, by application of at least one stress on the structure, such that walls facing two adjacent reliefs come into contact, thus generating at least one subsequent grating of reliefs of which at least one wall is slanted.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: September 27, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stefan Landis, Hubert Teyssedre
  • Patent number: 11450776
    Abstract: A method of forming an area of electric contact with a semiconductor region mainly made of germanium, comprising the forming of a first area made of a first intermetallic material where more than 70% of the non-metal atoms are silicon atoms. There is also described a device including such a contacting area.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: September 20, 2022
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Willy Ludurczak, Philippe Rodriguez, Jean-Michel Hartmann, Abdelkader Aliane, Zouhir Mehrez
  • Patent number: 11437532
    Abstract: The production process according to the invention consists of a nanometric scale transformation of the crystalline silicon in a hybrid arrangement buried within the crystal lattice of a silicon wafer, to improve the efficiency of the conversion of light into electricity, by means of hot electrons. All the parameters, procedures and steps involved in manufacturing giant photoconversion cells have been tested and validated separately, by producing twenty series of test devices. An example of the technology consists of manufacturing a conventional crystalline silicon photovoltaic cell with a single collection junction and completing the device thus obtained by an amorphizing ion implantation followed by a post-implantation thermal treatment.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: September 6, 2022
    Assignee: SEGTON ADVANCED TECHNOLOGY
    Inventor: Zbigniew Kuznicki
  • Patent number: 11430909
    Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
  • Patent number: 11430908
    Abstract: A method for removing an undesired coating from a front face of a crystalline silicon solar cell includes: S1: depositing an Al2O3 film, an SiO2 film, and an SiNx film on a back face of a silicon wafer to form a backside passivation film, and forming an undesired coating on an edge of the front face of the silicon wafer; S2: preparing an aqueous film on a surface of the backside passivation film of the product obtained in S1; S3: passing the product obtained in S2 through an acid tank to remove the undesired coating; S4: passing the product obtained in S3 through a water tank to remove a residual treatment solution; and S5: drying the product obtained in S4.
    Type: Grant
    Filed: April 11, 2021
    Date of Patent: August 30, 2022
    Assignee: ZHEJIANG AIKO SOLAR ENERGY TECHNOLOGY CO., LTD.
    Inventors: Huimin Wu, Xiaoming Zhang, Jiebin Fang, Kang-Cheng Lin, Daneng He, Gang Chen
  • Patent number: 11417766
    Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11411100
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Wei Wang, Chih-Chuan Yang, Yu-Kuan Lin, Choh Fei Yeap
  • Patent number: 11404325
    Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Aun Ng, Kuo-Cheng Chiang, Carlos H. Diaz, Jean-Pierre Colinge
  • Patent number: 11404590
    Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a composite layer disposed between the photosensitive member and the silicon layer and surrounding the photosensitive member, wherein the composite layer includes a first material and a second material different from the first material.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chan-Hong Chern
  • Patent number: 11398553
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ruei-Ping Lin, Kai-Di Tzeng, Chen-Ming Lee, Wei-Yang Lee
  • Patent number: 11393939
    Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material, a first concentration of the second material at a portion of the superlattice layer proximal to the photosensitive member is greater than a second concentration of the second material at a portion of the superlattice layer distal to the photosensitive member.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chan-Hong Chern, Weiwei Song, Chih-Chang Lin, Lan-Chou Cho, Min-Hsiang Hsu
  • Patent number: 11393940
    Abstract: A photodetector is provided. The photodetector includes a semiconductor layer, a first superlattice structure in the semiconductor layer, and a light absorption material above the first superlattice structure. The first superlattice structure includes vertically stacked pairs of silicon layer/first silicon germanium layer. The first silicon germanium layers are made of Si1-xGex, and x is the atomic percentage of germanium and 0.1?x?0.9.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11380824
    Abstract: The application discloses a light-emitting device including a carrier, a light-emitting element and a connecting structure. The carrier includes a first connecting portion and a first necking portion extended from the first connecting portion. The first connecting portion has a first width, and the first necking portion has a second width. The second width is less than the first width. The light-emitting element includes a first light-emitting layer being able to emit a first light and a first contacting electrode formed under the first light-emitting layer. The first contacting electrode is corresponded to the first connecting portion. The connecting structure includes a first electrical connecting portion and a protecting portion surrounding the first electrical connecting portion. The first electrical connecting portion is electrically connected to the first connecting portion and the first contacting electrode.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: July 5, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Ching-Tai Cheng, Shau-Yi Chen, Yih-Hua Renn, Wei-Shan Hu, Pei-Hsuan Lan
  • Patent number: 11380814
    Abstract: A dicing method for separating a wafer comprising a plurality of solar cells stack along at least one parting line, at least having the steps of: providing the wafer with a top, a bottom, an adhesive layer which is integrally bonded with the top and a cover glass layer which is integrally bonded with the adhesive layer, wherein the wafer includes a plurality of solar cell stacks, each having a germanium substrate layer forming the bottom of the wafer, a germanium sub-cell and at least two III-V sub-cells; creating a separating trench along the parting line by means of laser ablation, which extends from a bottom of the wafer through the wafer and the adhesive layer at least up to a top of the cover glass layer; and dividing the cover glass layer along the separating trench.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 5, 2022
    Assignee: AZUR SPACE Solar Power GmbH
    Inventors: Steffen Sommer, Wolfgang Koestler, Alexander Frey
  • Patent number: 11374145
    Abstract: Methods of fabricating solar cells using UV-curing of light-receiving surfaces of the solar cells, and the resulting solar cells, are described herein. In an example, a method of fabricating a solar cell includes forming a passivating dielectric layer on a light-receiving surface of a silicon substrate. The method also includes forming an anti-reflective coating (ARC) layer below the passivating dielectric layer. The method also includes exposing the ARC layer to ultra-violet (UV) radiation. The method also includes, subsequent to exposing the ARC layer to ultra-violet (UV) radiation, thermally annealing the ARC layer.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: June 28, 2022
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Yu-Chen Shen, Périne Jaffrennou, Gilles Olav Tanguy Sylvain Poulain, Michael C. Johnson, Seung Bum Rim