Patents Examined by Earl N. Taylor
  • Patent number: 10535812
    Abstract: A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 14, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Yuya Hasegawa, Satohiro Kigoshi
  • Patent number: 10535829
    Abstract: A quantum dot device including an anode and a cathode facing each other, a quantum dot layer between the anode and the cathode and electron auxiliary layer between the quantum dot layer and the cathode, wherein the electron auxiliary layer includes at least one nanoparticle represented by Chemical Formula 1 and at least one metal halide represented by Chemical Formula 2, and a display device.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Su Kim, Tae Ho Kim, Kun Su Park, Sung Woo Kim, Eun Joo Jang
  • Patent number: 10534233
    Abstract: The present disclosure provides an array substrate, a method for manufacturing the same, and a display device, which belongs to the field of display technology. The array substrate includes a metal electrode layer, a pad layer, a first insulating layer and a first transparent conductive layer, wherein: the pad layer includes a transparent conductive material, the metal electrode layer includes a conductive layer and protection layers formed on both surfaces of the conductive layer, and the pad layer is connected to the metal electrode layer; the first insulating layer is covered on the metal electrode layer and the pad layer, and the first transparent conductive layer is disposed on the first insulating layer; and a via hole is provided in the first insulating layer, and the first transparent conductive layer is connected to the pad layer through the via hole.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Maokun Tian, Zhonghao Huang, Xu Wu
  • Patent number: 10529872
    Abstract: A semiconductor system includes a silicon substrate and a porous silicon region disposed on the silicon substrate. The porous silicon region is configured to passivate the surface of the silicon substrate via a field effect and to reduce reflection loss on the silicon substrate via an appropriate refractive index. The porous silicon region is manufactured by a stain etching process, which retrofits existing tools for junction isolation and Phosphorus Silicon Glass (PSG) etch in solar cell manufacturing. The retrofitted tools for junction isolation and PSG etch achieves multiple purposes in a single step, including etch-back, PSG etch, antireflection coating, and passivation of the front surface of the solar cell.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 7, 2020
    Assignee: SPECMAT, Inc.
    Inventors: Horia M. Faur, Maria Faur
  • Patent number: 10529662
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha
  • Patent number: 10515993
    Abstract: An exemplary stacked photodetector assembly includes a first wafer and a second wafer bonded to the first wafer. The first wafer includes a SPAD and has a thickness T1 configured to minimize absorption by the first wafer of photons included in light incident upon the first wafer while the SPAD is in a disarmed state. The second wafer has a thickness T2 configured to provide structural support for the first wafer. The stacked photodetector assembly includes a fast gating circuit electrically coupled to the SPAD and configured to arm and disarm the SPAD.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 24, 2019
    Assignee: HI LLC
    Inventors: Ryan Field, Husam Katnani, Bruno Do Valle, Rong Jin, Jacob Dahle
  • Patent number: 10515894
    Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo, Nicole A. Saulnier
  • Patent number: 10510800
    Abstract: An integrated circuit is provided with a (bridge) rectifier circuit configured to couple to an alternating current (AC) supply to a (string of) LEDs monolithically fabricated on substrate, preferably on a patterned sapphire substrate (PSS). The rectifier including at least one schottky barrier diode configured to have a reverse-bias breakdown voltage substantially equal to or greater than half a peak voltage of the AC supply. Further embodiments include a method for fabricating an integrated Schottky barrier diode (SBD) with a LED on a LED wafer. Some embodiments can include etching processes to a wafer that may include a plurality of processing cycles. Some embodiments can further include a wafer having a patterned substrate. The wafer with the patterned substrate may have an interface layer configured to facilitate increasing a forward bias current density of the SBD.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: December 17, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Jie Liu, Jian Xu
  • Patent number: 10510894
    Abstract: A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yun Chang, Ming-Ching Chang, Shu-Yuan Ku
  • Patent number: 10510765
    Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Chi Wu, Chung-Jen Huang
  • Patent number: 10510825
    Abstract: A reliable metal insulator metal (MIM) capacitor is disclosed. The MIM capacitor is disposed over at least an interlevel dielectric (ILD) layer of a plurality of ILD layers with interconnects disposed over a substrate. The MIM capacitor includes a capacitor dielectric disposed between top and bottom metal capacitor electrodes. The edges of the top metal electrode at the interface with the capacitor dielectric are rounded. The rounded edges of the top capacitor electrode at the interface with the capacitor dielectric reduce edge electric field, thereby improves time-dependent dielectric breakdown (TDDB) reliability of the capacitor.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zhehui Wang, Hai Cong, Ramadas Nambatyathu
  • Patent number: 10510874
    Abstract: A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang, Keng-Chu Lin, Shi-Ning Ju
  • Patent number: 10504926
    Abstract: A thin film transistor, a method for fabricating the same, an array substrate, and a display panel are disclosed. The method includes: forming a semiconductor film comprising metallic elements, an etching stop film, and a source and drain film on a substrate in this order; and forming a pattern comprising an active layer, an etching stop layer, and a source and drain on the active layer by using a same mask plate, wherein the etching stop layer electrically connects the source and drain with the active layer. Since an etching stop film is formed on a semiconductor film comprising metallic elements, during etching the metal layer, the etching stop film can protect the semiconductor film comprising metallic elements from being etched, and this ensures the performance of the resultant active layer.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: December 10, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Qiang Zhou, Chaofan Zhu, Xingfeng Ren
  • Patent number: 10490767
    Abstract: An organic light-emitting diode includes a carrier; at least two electrodes; an organic layer sequence having at least one active zone that generates light; and light-opaque visual protection layers that have no influence on an emission characteristic of the organic layer sequence and the organic light-emitting diode, one of which is located directly on the carrier, the organic layer sequence is located between the two electrodes and one of the electrodes is attached directly to the carrier, the visual protection layer, viewed in a plan view, completely surrounds the organic layer sequence, at least one of the electrodes is provided with a structuring in a region adjacent to the organic layer sequence in a plan view, in a plan view, the structuring is located completely beside the organic layer sequence, and the structuring is hidden by the visual protection layer for a viewer from outside the organic light-emitting diode.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: November 26, 2019
    Assignee: OSRAM OLED GmbH
    Inventors: Nina Riegel, Daniel Riedel, Thomas Wehlus, Arne Flei├čner, Armin Heinrichsdobler
  • Patent number: 10486965
    Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 26, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Jan Edward Vandemeer, Jonathan Hale Hammond, Julio C. Costa
  • Patent number: 10490470
    Abstract: A method of fabricating a semiconductor package comprises providing a carrier, fabricating an opening in the carrier, attaching a semiconductor chip to the carrier and fabricating an encapsulation body covering the semiconductor chip.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Hock Heng Chong, Sook Woon Chan, Chau Fatt Chiang, Khar Foong Chung, Chee Hong Fang, Muhammat Sanusi Muhammad, Mei Chin Ng, Yean Seng Ng, Pei Luan Pok, Choon Huey Wang
  • Patent number: 10475757
    Abstract: A package structure includes at least one die, an antenna element, and at least one through interlayer via. The antenna element is located on the at least one die. The at least one through interlayer via is located between the antenna element and the at least one die, wherein the antenna element is electrically connected to the at least one die through the at least one through interlayer via.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Patent number: 10475750
    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces and a ground plane therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer; a heat pipe thermally interfaced to a top surface of the functional semiconductor die; one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heat pipe; in which the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; and further in which the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form. Other related embodiments are disclosed.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: November 12, 2019
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Pramod Malatkar
  • Patent number: 10461277
    Abstract: A display device according to the present invention includes a display region arranged with a plurality of pixels, and a sealing layer covering the display region, wherein the sealing layer includes an insulation layer having a density pattern, the density pattern is a pattern including a low density region and a high density region, the low density region has the insulation layer with a lower density than an average density within the display region of the insulation layer, and the high density region has the insulation layer with a higher density than an average density within the display region of the insulation layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 29, 2019
    Assignee: Japan Display Inc.
    Inventor: Hiraaki Kokame
  • Patent number: 10461154
    Abstract: A method of forming nanosheets that includes providing a stack of semiconductor material layers on a supporting bulk substrate. A first undercut region filled with a first dielectric material is formed extending from the opening into the bulk semiconductor substrate underlying the semiconductor material layers of the at least two stacks of semiconductor material layers. A second undercut region into the bulk semiconductor substrate filled with a second dielectric material from a side of the at least two stacks of semiconductor material layers that is opposite a side of the at least two stacks of semiconductor material layer at which the first undercut region is positioned. The first and second dielectric material merged that provide a full isolation region.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yi Song, Chi-Chun Liu, Zhenxing Bi, Shogo Mochizuki